Simulation Results: aes/masked

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.63 %
  • code
  • 93.66 %
  • assert
  • 98.23 %
  • func
  • 74.00 %
  • block
  • 94.35 %
  • line
  • 95.99 %
  • branch
  • 87.35 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 117.206us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 95.770us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 63.879us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 77.946us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 5340.784us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 123.047us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 79.679us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 77.946us 1 1 100.00
aes_csr_aliasing 2.000s 123.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 95.770us 1 1 100.00
aes_config_error 3.000s 70.286us 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 95.770us 1 1 100.00
aes_config_error 3.000s 70.286us 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 58.169us 1 1 100.00
aes_b2b 5.000s 212.420us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 95.770us 1 1 100.00
aes_config_error 3.000s 70.286us 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
aes_alert_reset 3.000s 162.156us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 196.726us 1 1 100.00
aes_config_error 3.000s 70.286us 1 1 100.00
aes_alert_reset 3.000s 162.156us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 441.549us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 1501.525us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 162.156us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 58.169us 1 1 100.00
aes_sideload 2.000s 57.336us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 573.600us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 16.000s 1795.488us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 98.917us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 167.864us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 167.864us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.879us 1 1 100.00
aes_csr_rw 2.000s 77.946us 1 1 100.00
aes_csr_aliasing 2.000s 123.047us 1 1 100.00
aes_same_csr_outstanding 1.000s 104.817us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.879us 1 1 100.00
aes_csr_rw 2.000s 77.946us 1 1 100.00
aes_csr_aliasing 2.000s 123.047us 1 1 100.00
aes_same_csr_outstanding 1.000s 104.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 426.050us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 253.538us 0 1 0.00
aes_control_fi 3.000s 81.165us 1 1 100.00
aes_cipher_fi 3.000s 161.393us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 188.904us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 188.904us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 188.904us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 188.904us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 105.401us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 643.742us 1 1 100.00
aes_tl_intg_err 3.000s 466.170us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 466.170us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 162.156us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 188.904us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 188.904us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 95.770us 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
aes_alert_reset 3.000s 162.156us 1 1 100.00
aes_core_fi 3.000s 113.199us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 70.286us 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
aes_core_fi 3.000s 113.199us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 188.904us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 75.030us 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 58.169us 1 1 100.00
aes_sideload 2.000s 57.336us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 75.030us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 75.030us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 75.030us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 75.030us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 75.030us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 58.169us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 253.538us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 253.538us 0 1 0.00
aes_control_fi 3.000s 81.165us 1 1 100.00
aes_cipher_fi 3.000s 161.393us 1 1 100.00
aes_ctr_fi 3.000s 221.399us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 253.538us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 253.538us 0 1 0.00
aes_control_fi 3.000s 81.165us 1 1 100.00
aes_cipher_fi 3.000s 161.393us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 161.393us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 253.538us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 253.538us 0 1 0.00
aes_control_fi 3.000s 81.165us 1 1 100.00
aes_ctr_fi 3.000s 221.399us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 253.538us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 253.538us 0 1 0.00
aes_control_fi 3.000s 81.165us 1 1 100.00
aes_cipher_fi 3.000s 161.393us 1 1 100.00
aes_ctr_fi 3.000s 221.399us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 162.156us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 253.538us 0 1 0.00
aes_control_fi 3.000s 81.165us 1 1 100.00
aes_cipher_fi 3.000s 161.393us 1 1 100.00
aes_ctr_fi 3.000s 221.399us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 253.538us 0 1 0.00
aes_control_fi 3.000s 81.165us 1 1 100.00
aes_cipher_fi 3.000s 161.393us 1 1 100.00
aes_ctr_fi 3.000s 221.399us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 253.538us 0 1 0.00
aes_control_fi 3.000s 81.165us 1 1 100.00
aes_ctr_fi 3.000s 221.399us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 253.538us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 253.538us 0 1 0.00
aes_control_fi 3.000s 81.165us 1 1 100.00
aes_cipher_fi 3.000s 161.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 1.905us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 114180676497889713250176449369392939571296839507966597858693082475228908282642 4320
UVM_INFO @ 426050377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 17811270830876511123672502467972047659040300257812043317326837689099401704449 14180
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 97098672004786122241731052590393015009607135088703367608254551778617427603173 109
UVM_INFO @ 1905412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---