Simulation Results: aes/unmasked

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.41 %
  • code
  • 89.54 %
  • assert
  • 97.73 %
  • func
  • 74.95 %
  • block
  • 89.38 %
  • line
  • 91.58 %
  • branch
  • 79.69 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 382.256us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 77.293us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 87.276us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 131.398us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 252.445us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 252.178us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 57.718us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 131.398us 1 1 100.00
aes_csr_aliasing 3.000s 252.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 77.293us 1 1 100.00
aes_config_error 2.000s 80.009us 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 77.293us 1 1 100.00
aes_config_error 2.000s 80.009us 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 81.365us 1 1 100.00
aes_b2b 2.000s 69.005us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 77.293us 1 1 100.00
aes_config_error 2.000s 80.009us 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
aes_alert_reset 3.000s 191.825us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 62.068us 1 1 100.00
aes_config_error 2.000s 80.009us 1 1 100.00
aes_alert_reset 3.000s 191.825us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 275.547us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 367.085us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 191.825us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 81.365us 1 1 100.00
aes_sideload 2.000s 151.809us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 73.290us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 15.000s 1248.833us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 72.461us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 522.818us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 522.818us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 87.276us 1 1 100.00
aes_csr_rw 1.000s 131.398us 1 1 100.00
aes_csr_aliasing 3.000s 252.178us 1 1 100.00
aes_same_csr_outstanding 2.000s 315.848us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 87.276us 1 1 100.00
aes_csr_rw 1.000s 131.398us 1 1 100.00
aes_csr_aliasing 3.000s 252.178us 1 1 100.00
aes_same_csr_outstanding 2.000s 315.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 137.727us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 2.000s 176.657us 0 1 0.00
aes_control_fi 12.000s 10005.539us 0 1 0.00
aes_cipher_fi 1.000s 66.953us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 70.209us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 70.209us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 70.209us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 70.209us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 245.584us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 345.050us 1 1 100.00
aes_tl_intg_err 3.000s 843.974us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 843.974us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 191.825us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 70.209us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 70.209us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 77.293us 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
aes_alert_reset 3.000s 191.825us 1 1 100.00
aes_core_fi 2.000s 206.758us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 80.009us 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
aes_core_fi 2.000s 206.758us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 70.209us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 75.080us 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 81.365us 1 1 100.00
aes_sideload 2.000s 151.809us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 75.080us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 75.080us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 75.080us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 75.080us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 75.080us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 81.365us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 176.657us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 2.000s 176.657us 0 1 0.00
aes_control_fi 12.000s 10005.539us 0 1 0.00
aes_cipher_fi 1.000s 66.953us 1 1 100.00
aes_ctr_fi 1.000s 69.805us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 176.657us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 2.000s 176.657us 0 1 0.00
aes_control_fi 12.000s 10005.539us 0 1 0.00
aes_cipher_fi 1.000s 66.953us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 66.953us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 176.657us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 2.000s 176.657us 0 1 0.00
aes_control_fi 12.000s 10005.539us 0 1 0.00
aes_ctr_fi 1.000s 69.805us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 176.657us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 2.000s 176.657us 0 1 0.00
aes_control_fi 12.000s 10005.539us 0 1 0.00
aes_cipher_fi 1.000s 66.953us 1 1 100.00
aes_ctr_fi 1.000s 69.805us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 191.825us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 2.000s 176.657us 0 1 0.00
aes_control_fi 12.000s 10005.539us 0 1 0.00
aes_cipher_fi 1.000s 66.953us 1 1 100.00
aes_ctr_fi 1.000s 69.805us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 2.000s 176.657us 0 1 0.00
aes_control_fi 12.000s 10005.539us 0 1 0.00
aes_cipher_fi 1.000s 66.953us 1 1 100.00
aes_ctr_fi 1.000s 69.805us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 2.000s 176.657us 0 1 0.00
aes_control_fi 12.000s 10005.539us 0 1 0.00
aes_ctr_fi 1.000s 69.805us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 176.657us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 2.000s 176.657us 0 1 0.00
aes_control_fi 12.000s 10005.539us 0 1 0.00
aes_cipher_fi 1.000s 66.953us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 18.568us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 91188306454175541498230190937711242243847822623470168980768972826265631321060 6205
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 75575461233376355598086480889308839315794759061989630885936544033894589102169 151
UVM_INFO @ 10005539441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 96903494157942935994735009268221009931895467858858320784734184759833492179998 135
UVM_INFO @ 18567607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---