Simulation Results

Simulation Results: chip

02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
74.15 %

code
83.81 %

assert
97.37 %

func
41.27 %

line
94.02 %

branch
92.43 %

cond
88.28 %

toggle
87.20 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		76.90%
V2S		50.00%
V3		65.38%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	173.120s	2799.132us	1	1	100.00
	chip_sw_example_rom	78.320s	2406.059us	1	1	100.00
	chip_sw_example_manufacturer	147.920s	3070.160us	1	1	100.00
	chip_sw_example_concurrency	157.940s	2983.871us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	307.970s	7281.837us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	414.560s	5328.352us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2177.680s	31570.950us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3095.210s	31104.965us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	392.170s	6500.394us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3095.210s	31104.965us	1	1	100.00
	chip_csr_rw	414.560s	5328.352us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	7.160s	172.522us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	310.760s	4302.090us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	310.760s	4302.090us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	310.760s	4302.090us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	353.770s	4257.511us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	353.770s	4257.511us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	377.530s	4336.072us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	379.990s	4705.828us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	352.570s	4195.631us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1099.980s	8749.650us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1081.150s	8108.503us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	276.730s	4850.416us	1	1	100.00

213/277 passed

76.90 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	184.740s	5728.194us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	184.740s	5728.194us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	149.120s	2957.019us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	287.840s	6597.477us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	227.070s	4764.976us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	84.180s	2259.185us	1	1	100.00
	chip_tap_straps_testunlock0	298.810s	5866.683us	1	1	100.00
	chip_tap_straps_rma	465.830s	8860.924us	1	1	100.00
	chip_tap_straps_prod	75.490s	2692.513us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	435.270s	5040.172us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	435.270s	5040.172us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	645.880s	8557.471us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1748.380s	14555.974us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	355.220s	4260.347us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	574.800s	6114.879us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3934.530s	18850.302us	1	1	100.00
	chip_sw_aes_enc_jitter_en	186.810s	3180.097us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	811.560s	7925.252us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	154.040s	3075.382us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1634.430s	12671.043us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	177.640s	2940.994us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	399.260s	5831.877us	1	1	100.00
	chip_sw_clkmgr_jitter	166.400s	3485.213us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	188.870s	2786.914us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	536.980s	8485.707us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	245.360s	4885.034us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	169.450s	2862.082us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	245.360s	4885.034us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	177.110s	3358.899us	1	1	100.00
	chip_sw_aes_smoketest	175.640s	2648.891us	1	1	100.00
	chip_sw_aon_timer_smoketest	240.820s	3506.612us	1	1	100.00
	chip_sw_clkmgr_smoketest	110.240s	2963.694us	1	1	100.00
	chip_sw_csrng_smoketest	160.460s	3031.869us	1	1	100.00
	chip_sw_entropy_src_smoketest	732.110s	6210.818us	1	1	100.00
	chip_sw_gpio_smoketest	206.330s	2965.681us	1	1	100.00
	chip_sw_hmac_smoketest	180.000s	3890.814us	1	1	100.00
	chip_sw_kmac_smoketest	191.220s	3263.256us	1	1	100.00
	chip_sw_otbn_smoketest	1578.910s	11337.901us	1	1	100.00
	chip_sw_pwrmgr_smoketest	352.510s	5690.582us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	236.460s	6009.239us	1	1	100.00
	chip_sw_rv_plic_smoketest	187.280s	3086.190us	1	1	100.00
	chip_sw_rv_timer_smoketest	150.640s	2934.571us	1	1	100.00
	chip_sw_rstmgr_smoketest	108.530s	2628.223us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	148.690s	3264.018us	1	1	100.00
	chip_sw_uart_smoketest	152.420s	2989.490us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	135.160s	2559.811us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	297.380s	4999.376us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7797.060s	59580.800us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3146.020s	14801.865us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	97.248s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	1003.570s	14935.882us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	553.810s	14780.467us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7177.140s	52222.546us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7261.580s	53997.987us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	42.830s	1786.322us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	42.830s	1786.322us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3095.210s	31104.965us	1	1	100.00
	chip_same_csr_outstanding	1709.930s	16090.406us	1	1	100.00
	chip_csr_hw_reset	307.970s	7281.837us	1	1	100.00
	chip_csr_rw	414.560s	5328.352us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3095.210s	31104.965us	1	1	100.00
	chip_same_csr_outstanding	1709.930s	16090.406us	1	1	100.00
	chip_csr_hw_reset	307.970s	7281.837us	1	1	100.00
	chip_csr_rw	414.560s	5328.352us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	25.700s	457.032us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.790s	46.630us	1	1	100.00
	xbar_smoke_large_delays	46.010s	8243.206us	1	1	100.00
	xbar_smoke_slow_rsp	36.440s	3431.286us	1	1	100.00
	xbar_random_zero_delays	20.960s	299.159us	1	1	100.00
	xbar_random_large_delays	213.710s	37275.760us	1	1	100.00
	xbar_random_slow_rsp	166.560s	18221.683us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	32.500s	1212.664us	1	1	100.00
	xbar_error_and_unmapped_addr	42.020s	1103.131us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	30.350s	557.154us	1	1	100.00
	xbar_error_and_unmapped_addr	42.020s	1103.131us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	5.500s	78.174us	1	1	100.00
	xbar_access_same_device_slow_rsp	419.770s	52346.258us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	36.970s	1601.016us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	83.680s	1661.526us	1	1	100.00
	xbar_stress_all_with_error	134.910s	6335.643us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	254.130s	2488.340us	1	1	100.00
	xbar_stress_all_with_reset_error	53.750s	391.270us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3146.020s	14801.865us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2609.080s	33370.780us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3031.030s	14358.314us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	118.921s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	33.175s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	11.116s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	7.988s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	20.628s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	120.333s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.442s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	9.520s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	35.689s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.428s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	131.534s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	57.748s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	39.963s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	39.285s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.520s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	20.380s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	23.590s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	20.310s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	19.020s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	20.250s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.730s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	23.980s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	24.580s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	22.370s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	23.660s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.300s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	19.270s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.090s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	19.990s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.290s	10.380us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	128.266s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	11.582s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	7.669s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	7.572s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	20.216s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	5939.310s	29014.345us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	3222.450s	16970.657us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	6033.230s	31152.413us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	2984.360s	15124.943us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3200.440s	34148.830us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3200.440s	34148.830us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	169.360s	3029.368us	1	1	100.00
	chip_sw_aes_enc_jitter_en	186.810s	3180.097us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	188.080s	2872.127us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	161.070s	3063.902us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1427.390s	11187.172us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	176.090s	3026.079us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	299.360s	5022.320us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	426.400s	5289.410us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	469.810s	5406.401us	1	1	100.00
	chip_plic_all_irqs_10	240.180s	3666.765us	1	1	100.00
	chip_plic_all_irqs_20	279.820s	4212.296us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	178.170s	2931.289us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1150.720s	14140.020us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	253.410s	4212.432us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	182.580s	2486.686us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.144s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	626.960s	7228.697us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	698.050s	6384.474us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	867.300s	7899.749us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9382.050s	254984.737us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	245.720s	4200.127us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	352.510s	5690.582us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	245.720s	4200.127us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	327.880s	8447.080us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	327.880s	8447.080us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	308.250s	6658.777us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	368.950s	4583.278us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	570.110s	6755.892us	1	1	100.00
	chip_sw_aes_idle	161.070s	3063.902us	1	1	100.00
	chip_sw_hmac_enc_idle	159.920s	2864.860us	1	1	100.00
	chip_sw_kmac_idle	146.930s	3056.977us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	291.000s	5033.891us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	266.680s	4414.967us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	273.500s	4512.749us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	270.040s	4579.046us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	818.650s	10721.057us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	376.770s	4457.769us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	418.900s	5363.477us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	430.960s	4247.550us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	359.950s	4485.463us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	429.860s	4516.202us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	414.330s	4859.190us	1	1	100.00
	chip_sw_ast_clk_outputs	645.880s	8557.471us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	305.610s	5887.260us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	430.960s	4247.550us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	359.950s	4485.463us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	355.220s	4260.347us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	574.800s	6114.879us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3934.530s	18850.302us	1	1	100.00
	chip_sw_aes_enc_jitter_en	186.810s	3180.097us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	811.560s	7925.252us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	154.040s	3075.382us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1634.430s	12671.043us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	177.640s	2940.994us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	399.260s	5831.877us	1	1	100.00
	chip_sw_clkmgr_jitter	166.400s	3485.213us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	125.570s	2568.978us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	376.730s	5098.573us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	607.380s	6765.674us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4145.040s	24758.233us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	158.010s	2604.461us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	183.760s	3170.420us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	797.410s	9098.085us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	183.840s	3302.670us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	316.820s	4570.542us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1265.600s	21163.829us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	3462.970s	25940.516us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	645.880s	8557.471us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	341.110s	4286.599us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	246.860s	3538.899us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	426.400s	5289.410us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	626.960s	7228.697us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1097.520s	8509.389us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	361.520s	4277.016us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	546.350s	7182.721us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	224.250s	3697.223us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2958.110s	18034.138us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	167.040s	3338.603us	1	1	100.00
	chip_sw_edn_entropy_reqs	655.130s	6577.160us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	167.040s	3338.603us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1097.520s	8509.389us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	137.670s	3392.304us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1322.000s	26363.238us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	490.690s	5138.690us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	574.800s	6114.879us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	319.770s	4495.990us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	355.220s	4260.347us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3182.220s	45079.935us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1322.000s	26363.238us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	203.030s	2994.502us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1495.660s	12334.747us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.800s	2893.264us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3182.220s	45079.935us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.800s	2893.264us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.800s	2893.264us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.800s	2893.264us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	152.800s	2893.264us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	426.400s	5289.410us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	90.070s	3555.386us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	533.960s	5491.760us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	441.040s	5904.651us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	441.040s	5904.651us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	189.590s	2525.117us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	154.040s	3075.382us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	159.920s	2864.860us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1121.500s	8790.294us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1805.530s	12018.408us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	400.910s	5575.788us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	475.260s	5098.847us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	416.630s	4976.755us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	292.580s	3842.953us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1495.660s	12334.747us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1634.430s	12671.043us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1533.660s	10894.626us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1427.390s	11187.172us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	5462.110s	20026.780us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	145.440s	3402.770us	1	1	100.00
	chip_sw_kmac_mode_kmac	218.390s	2988.270us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	177.640s	2940.994us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1495.660s	12334.747us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	373.450s	7116.802us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	113.810s	2647.429us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1156.060s	8866.700us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	146.930s	3056.977us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	299.360s	5022.320us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	84.180s	2259.185us	1	1	100.00
	chip_tap_straps_rma	465.830s	8860.924us	1	1	100.00
	chip_tap_straps_prod	75.490s	2692.513us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	175.710s	2985.421us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	373.450s	7116.802us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	373.450s	7116.802us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	373.450s	7116.802us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1220.280s	10619.392us	1	1	100.00
chip_sw_lc_ctrl_broadcast				20	22	90.91
	chip_sw_flash_ctrl_lc_rw_en	152.800s	2893.264us	0	1	0.00
	chip_sw_flash_rma_unlocked	3182.220s	45079.935us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	215.560s	2731.036us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	426.040s	6598.675us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	454.410s	5650.350us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	564.660s	6004.265us	0	1	0.00
	chip_sw_lc_ctrl_transition	373.450s	7116.802us	1	1	100.00
	chip_sw_keymgr_key_derivation	1495.660s	12334.747us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	361.660s	8389.403us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	611.330s	9395.111us	1	1	100.00
	chip_prim_tl_access	90.070s	3555.386us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	305.610s	5887.260us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	376.770s	4457.769us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	418.900s	5363.477us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	430.960s	4247.550us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	359.950s	4485.463us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	429.860s	4516.202us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	414.330s	4859.190us	1	1	100.00
	chip_tap_straps_dev	84.180s	2259.185us	1	1	100.00
	chip_tap_straps_rma	465.830s	8860.924us	1	1	100.00
	chip_tap_straps_prod	75.490s	2692.513us	1	1	100.00
	chip_rv_dm_lc_disabled	317.640s	14485.264us	1	1	100.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	196.930s	3841.355us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	81.020s	3940.918us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	77.470s	3438.942us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	166.490s	3903.059us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	2163.310s	54406.975us	0	1	0.00
	chip_rv_dm_lc_disabled	317.640s	14485.264us	1	1	100.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	711.700s	9597.079us	0	1	0.00
	chip_sw_lc_walkthrough_prod	598.750s	8566.197us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	655.450s	10206.295us	1	1	100.00
	chip_sw_lc_walkthrough_rma	436.620s	7492.467us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	2163.310s	54406.975us	0	1	0.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	59.530s	2006.673us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	73.270s	2761.781us	1	1	100.00
	rom_volatile_raw_unlock	112.409s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3857.110s	17640.777us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3934.530s	18850.302us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	570.110s	6755.892us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	570.110s	6755.892us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	570.110s	6755.892us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	269.250s	3651.165us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	373.450s	7116.802us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1322.000s	26363.238us	1	1	100.00
	chip_sw_otbn_mem_scramble	269.250s	3651.165us	1	1	100.00
	chip_sw_keymgr_key_derivation	1495.660s	12334.747us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	381.740s	5396.863us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	153.340s	2575.472us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1322.000s	26363.238us	1	1	100.00
	chip_sw_otbn_mem_scramble	269.250s	3651.165us	1	1	100.00
	chip_sw_keymgr_key_derivation	1495.660s	12334.747us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	381.740s	5396.863us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	153.340s	2575.472us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	373.450s	7116.802us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	393.650s	4907.364us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	175.710s	2985.421us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	215.560s	2731.036us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	426.040s	6598.675us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	454.410s	5650.350us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	564.660s	6004.265us	0	1	0.00
	chip_sw_lc_ctrl_transition	373.450s	7116.802us	1	1	100.00
	chip_prim_tl_access	90.070s	3555.386us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	90.070s	3555.386us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	880.140s	7446.601us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	63.400s	2547.568us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1108.040s	26435.799us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	259.220s	7457.712us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	324.050s	7096.521us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	445.920s	7770.860us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	930.880s	21656.570us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	1074.750s	15109.832us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	327.880s	8447.080us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	986.620s	10539.403us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	338.650s	5608.434us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	63.400s	2547.568us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	274.080s	4635.929us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	505.780s	10189.568us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	327.880s	7792.060us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	134.460s	2789.747us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1436.350s	19037.035us	1	1	100.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	551.940s	7121.532us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	977.140s	12174.922us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	2129.770s	32366.155us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	163.260s	3697.031us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	426.400s	5289.410us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	361.660s	8389.403us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	361.660s	8389.403us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				4	4	100.00
	chip_sw_pwrmgr_all_reset_reqs	977.140s	12174.922us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1436.350s	19037.035us	1	1	100.00
	chip_sw_pwrmgr_wdog_reset	338.650s	5608.434us	1	1	100.00
	chip_sw_pwrmgr_smoketest	352.510s	5690.582us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	326.900s	5377.104us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	323.110s	4661.415us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	291.970s	4648.760us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1150.720s	14140.020us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	158.040s	3075.267us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	426.400s	5289.410us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	698.050s	6384.474us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	492.050s	4952.419us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	473.580s	4617.476us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	156.520s	2862.453us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	153.340s	2575.472us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	323.110s	4661.415us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	323.110s	4661.415us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	168.580s	3285.019us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	692.100s	10153.058us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	805.320s	13938.523us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	326.900s	5377.104us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	175.050s	3319.105us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	1349.770s	13646.349us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	465.830s	8860.924us	1	1	100.00
chip_rv_dm_lc_disabled				1	1	100.00
	chip_rv_dm_lc_disabled	317.640s	14485.264us	1	1	100.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	469.810s	5406.401us	1	1	100.00
	chip_plic_all_irqs_10	240.180s	3666.765us	1	1	100.00
	chip_plic_all_irqs_20	279.820s	4212.296us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	191.360s	3156.361us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	140.290s	2664.930us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3146.020s	14801.865us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	466.320s	7579.076us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	214.850s	3360.879us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	224.350s	3431.315us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	195.670s	3176.404us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	381.740s	5396.863us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	399.260s	5831.877us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	513.610s	10293.359us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	402.680s	7577.681us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	611.330s	9395.111us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	426.400s	5289.410us	1	1	100.00
	chip_sw_data_integrity_escalation	435.270s	5040.172us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	551.940s	7121.532us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	991.810s	24581.120us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	169.650s	3261.082us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	190.940s	2937.051us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	359.440s	4748.792us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	991.810s	24581.120us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	991.810s	24581.120us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2226.700s	20161.776us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2226.700s	20161.776us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	407.100s	6752.133us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3200.440s	34148.830us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	181.090s	3173.259us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	140.550s	3009.867us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	260.570s	3225.172us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	312.150s	4571.905us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	965.420s	7931.106us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5504.640s	31616.401us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1856.470s	12635.046us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	158.780s	3081.736us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	202.420s	2856.021us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	128.540s	2761.580us	0	1	0.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9363.290s	68746.961us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1130.480s	6532.884us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	589.040s	14572.664us	0	1	0.00
	rom_e2e_jtag_debug_dev	170.220s	3417.760us	0	1	0.00
	rom_e2e_jtag_debug_rma	177.210s	5002.540us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	65.340s	1739.905us	0	1	0.00
	rom_e2e_jtag_inject_dev	233.180s	5143.040us	0	1	0.00
	rom_e2e_jtag_inject_rma	74.290s	2701.580us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	30.357s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	287.880s	3263.756us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	322.600s	3079.340us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	513.990s	4004.162us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	891.040s	7230.508us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	229.180s	2542.472us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	592.890s	5051.903us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	48.410s	2117.919us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	167.070s	3122.546us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	271.110s	5875.632us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	339.670s	5356.937us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	977.140s	12174.922us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	589.040s	14572.664us	0	1	0.00
	rom_e2e_jtag_debug_dev	170.220s	3417.760us	0	1	0.00
	rom_e2e_jtag_debug_rma	177.210s	5002.540us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	356.890s	4953.172us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	426.400s	5289.410us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5354.290s	37986.836us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5354.290s	37986.836us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	190.030s	3756.899us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	353.770s	4257.511us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3264.470s	19696.369us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	198.810s	2821.898us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	18.530s	10.240us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	6.250s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	143.930s	2662.267us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	133.500s	3162.474us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	251.960s	4425.861us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	9.558s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	153.190s	3149.740us	1	1	100.00
	ate_bootstrap_flash_erase	601.350s	10010.220us	0	1	0.00
	ate_bootstrap_one_frame	6391.730s	43454.317us	1	1	100.00
	ate_bootstrap_disjoint	9579.410s	79709.458us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	39841900336995692679445438197571212287669983871909926798439805254120087677945	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34413650027830421510267847403511342671401060361574360958613016487068314537574	None	Another command (pid=571849) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=466221) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=573107) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	42120898501223072032743378431360847705722565878904479965845972266629980848324	None	Another command (pid=477906) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=673210) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=664774) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	62786236006527524938156223522604084894599005751235065956498265399111013850827	None	Another command (pid=619384) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=601818) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=594168) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	115000260607961051324793349690139180675571398489978623499062249091341993847955	None	---- STDERR ---- Another command (pid=576674) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	39162974310475253294807197000355591166595919304709312088916574762363256840433	None	Another command (pid=654219) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=605401) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=422806) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	83754263226483360500528087670116482223274120508657353561941055950061130878561	None	Another command (pid=571849) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=466221) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=440290) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	99476088983460583218211158734061048115499002780733369600074270885866909598547	None	Another command (pid=581637) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=600047) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=450892) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	54498556906862567562835703154352066021954899976344595289798070951426284475729	None	---- STDERR ---- Another command (pid=582343) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=581637) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	43148873767428181127866089387866936597226360992741470978240320865515169754676	None	Another command (pid=594226) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=605401) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=422806) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	22534899027686869223173219380680387745347751411257083617862344298207592845529	None	Another command (pid=585819) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=597834) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=587686) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	7431992481846953775553606963933291289536119746129843812387197858876307767797	None	Another command (pid=572038) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=574063) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=584279) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	83555212618649253678987981722287158094649704732743307566719748488290070722858	None	Another command (pid=693023) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=685587) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=679462) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	55632241570370303738677313798806451541252558939587287951645341882358621341721	None	Another command (pid=605401) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=422806) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=632158) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	32542616337181527464991735144146391826506589969271177256697612790470394285582	None	Another command (pid=654219) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=605401) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=422806) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	24630716706258133913479124854020880249123799183802712268051475866507241812341	None	---- STDERR ---- Another command (pid=587686) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	109561129064401671615142184641168663617392684230437021372807413432023477394678	None	Another command (pid=571849) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=466221) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=440290) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	91005980918408281484515488030810526356490842278603026837738634612086715539525	None	Another command (pid=440290) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=463555) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=575701) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	62147283008907345489725203099917614704069733317206373376295083864144816788687	None	---- STDERR ---- Another command (pid=403006) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	49444342027395111096905033033901032143331474611110116228812699147333189029420	None	---- STDERR ---- Another command (pid=584279) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	19946799490184977539443093871144631035704732824754330684756907846276036697533	None	Another command (pid=587686) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=606645) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=446693) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	33487810449242869263675025872215076738190032449939810786016974912896111545478	None	Another command (pid=585819) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=587686) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=607585) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	106498828316490964121384399186335854474581882441024764890205546926359302210736	None	Another command (pid=565632) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=571849) is running. Waiting for it to complete on the server (server_pid=292917)... Another command (pid=466221) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	11244178635586171792004602106375381575667782591040604120321904086418270897933	None	---- STDERR ---- Another command (pid=379367) is running. Waiting for it to complete on the server (server_pid=292917)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	6091308233917626382252753684876749111892813551486464002442760698066610123971	368	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	108311432170160081404963856010529759825035524441285548969016828338097056283605	368	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	31519508725148018466852594466503355868636250573146013657774081116328414721722	366	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	43099978149069653334555057994452107893726620558409341907834965025139047787912	325	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	24130312263306337692283380847234003594701208376518412386994212666797816843968	325	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	45102464233301387155026531020526971245593433900388582241840175158913597992257	326	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access				5 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	93485169354397302094813379208698626487982547831675088114120443718138839844964	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	109156119881580889828200121573148533491326282325728291325135857745544661402767	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	99187919349587876561770862660738918265894487610544232814350288532999733848008	307	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	73575749656007914825527987400395712600477363121686016685680052859837797734582	310	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	17591822917329698026718963342713140674458743550720876539813030289469099094623	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	4435884156209889453526132145156947138460147756878584141481372053293473070015	369	UVM_INFO @ 9597.079080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	12522167511733741583320526634712724354630968016713844065276459204242942979448	369	UVM_INFO @ 8566.197351 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	38401685954865260237258356232555187174684949301122308537120311201690968160287	341	UVM_INFO @ 7492.467396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				3 test runs
	chip_sw_pwrmgr_deep_sleep_por_reset	107696444157695040726875059754835087928355449970220772925806434774551452641247	325	UVM_ERROR @ 7096.521500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7096.521500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	34469423201190953898505219637520171946826112620786535904265560698870697285965	343	UVM_ERROR @ 10189.568000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 10189.568000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	113091685321199111161903807904156151732133954880422559885586916329624397567206	319	UVM_ERROR @ 8447.080000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8447.080000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	69701248910335811694715178521358974733776381659948737541545404385967705266128	328	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	52393263967548773464138444373746566842741700199784762769626263986906682763635	328	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	110582466314356174759949425034019971961247289778551336043283840654819659371072	328	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_multistream	89736463073417579442331924896796570234373111258991624591927777319070546117990	386	UVM_INFO @ 12018.407934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	89786367521736266648913653408159414175270490598418435563266486194018121131237	338	UVM_INFO @ 20026.779781 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	31102416885661658890362174208631805829292959493037656883133736900497570657252	364	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	114907982935893105132893511977159366794350166968618492620425656606355275898431	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	52271002723795790329491046198402054044575412765703886609731559526924517007179	365	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	23658237948336813898036259813854495943616725011039060709445688809759292033665	326	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	22980864499188887590084913890958747530605212584342054700083170950794091821299	301	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]				1 test run
	chip_sw_sleep_pin_mio_dio_val	45231353273624155272524137783596645896420145201944403251940510478956244925077	451	UVM_INFO @ 2957.018500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	102536718458397946366171819225370234955214988000768216487101117062842949622559	332	UVM_INFO @ 3360.879422 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	9146248565999482720290001023327952957775543376617250295307161236321574646120	309	UVM_INFO @ 2893.263632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	92534542274933725809239800658937584698996608498045435741388678333646073519260	342	UVM_INFO @ 6004.264982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	54262001941524420405470521572412541869141576506397499589392042754281996063554	316	UVM_ERROR @ 3122.545986 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3122.545986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	51842395449698445270263171708951154264601800448251637663577961352591395782986	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_walkthrough_testunlocks	91439977618090431653911413876087682705246243692323774434612876153132998519960	497	UVM_INFO @ 54406.975056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	106756267645759079170301586197224528842394815011895041670446646410961103154824	303	UVM_ERROR @ 2547.567684 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2547.567684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	17839981382363477297605522393020014445932271480863800718839542122794608293912	313	UVM_ERROR @ 2789.746898 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2789.746898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	25149443912452798336956187269203704332629765966491923461068565957238498475731	332	UVM_INFO @ 34148.829785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:342)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	47774589027319276832570180565195371107352564251540530333337620283216214757621	307	UVM_INFO @ 3026.078538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	31481643160246309183640318419000461073880138645471530054884014103332123372223	308	UVM_INFO @ 2486.686435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	99666234145788449211127435581019888102237980721747122905225680207480274073526	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_tl_errors	93759301490643143837687952784892174034274150310274701542065407437822475264442	217	TL item was: req: (cip_tl_seq_item@30242) { a_addr: 'h105e0 a_data: 'h893a764d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h1924c d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 1786.322132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	43851469253997605272990089714316218445264232326318840803716764786836008759865	343	UVM_INFO @ 3263.755989 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.				1 test run
	chip_sw_rv_dm_access_after_wakeup	89937190361899322003677673812469156568875880441977377487153754769486151465330	329	UVM_INFO @ 13646.349432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.				1 test run
	chip_sw_rv_core_ibex_lockstep_glitch	109569914548617728792939432611712499666083053092183434323953162593448855389401	329	UVM_INFO @ 2761.580184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_idle_load	67246177901091813886173862026280205319923560905011209959330150872913023962098	318	UVM_INFO @ 14935.881905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_sleep_load	28841345438536451702199802931334395601768477693828796059460062870689514538303	337	UVM_INFO @ 14780.467201 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	6914232988863173841047055109479609959835981010072472146712087693887702264261	327	UVM_INFO @ 14555.973677 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	66401070491702230833107234275772022512180363294847457064761321612933872767617	272	UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	20249931064147169146122348578702033044413011874308984237249071223889555714334	325	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	53462972972232933985851537117642620112363189418678245882757374846912238541924	325	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!				1 test run
	rom_e2e_jtag_debug_test_unlocked0	34836322950648417003049900093124449331203157878921211836871544505027662965083	330	UVM_INFO @ 14572.664488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds				1 test run
	rom_e2e_jtag_debug_dev	37740315365054786722049827068513617647482109457783019112309762714749566134903	318	UVM_INFO @ 3417.760234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_no_meas	17851826711661225834141099132335754460091915742584294224290583770434393188324	319	UVM_INFO @ 16970.656696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	9819502191233796460792314128575895635003770945261135000102126383406877937249	327	UVM_ERROR @ 4999.376314 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4999.376314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---