Simulation Results: clkmgr

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.30 %
  • code
  • 97.76 %
  • assert
  • 94.07 %
  • func
  • 85.08 %
  • line
  • 98.88 %
  • branch
  • 98.59 %
  • cond
  • 92.12 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.800s 22.607us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.800s 14.991us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.720s 15.906us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 13.700s 5192.748us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.380s 45.536us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.140s 131.522us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.720s 15.906us 1 1 100.00
clkmgr_csr_aliasing 1.380s 45.536us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.040s 204.454us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.930s 37.552us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.750s 23.221us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.870s 73.790us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.800s 22.607us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 2.600s 323.822us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.690s 1577.295us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 2.600s 323.822us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 0.870s 76.159us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.790s 43.507us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.120s 274.880us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.120s 274.880us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.800s 14.991us 1 1 100.00
clkmgr_csr_rw 0.720s 15.906us 1 1 100.00
clkmgr_csr_aliasing 1.380s 45.536us 1 1 100.00
clkmgr_same_csr_outstanding 1.340s 63.351us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.800s 14.991us 1 1 100.00
clkmgr_csr_rw 0.720s 15.906us 1 1 100.00
clkmgr_csr_aliasing 1.380s 45.536us 1 1 100.00
clkmgr_same_csr_outstanding 1.340s 63.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 25.240s 10090.272us 0 1 0.00
clkmgr_tl_intg_err 2.020s 214.627us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 447.830s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 447.830s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 447.830s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 447.830s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.420s 700.387us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.020s 214.627us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 2.600s 323.822us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.690s 1577.295us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 447.830s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.900s 35.169us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.380s 351.194us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.900s 22.335us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.990s 81.766us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.750s 29.683us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.720s 15.906us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 25.240s 10090.272us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.720s 15.906us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.720s 15.906us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 25.240s 10090.272us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 0.890s 116.698us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 57.460s 10760.678us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 33337414496388044346589696210661299043954725741731585090892678000960231858595 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 82644336530355020372041510133797497535792864256487703198220858364119130074340 110
UVM_INFO @ 10090271573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---