Simulation Results: edn/edn0

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.32 %
  • code
  • 83.21 %
  • assert
  • 97.61 %
  • func
  • 81.15 %
  • line
  • 97.77 %
  • branch
  • 92.47 %
  • cond
  • 87.75 %
  • toggle
  • 86.43 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 15.169us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 41.921us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 42.411us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.760s 145.724us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.050s 248.731us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.870s 31.701us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 42.411us 1 1 100.00
edn_csr_aliasing 1.050s 248.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.360s 318.458us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.360s 318.458us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.360s 318.458us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 20.473us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.160s 164.121us 1 1 100.00
errs 1 1 100.00
edn_err 0.940s 45.103us 1 1 100.00
disable 2 2 100.00
edn_disable 0.970s 14.897us 1 1 100.00
edn_disable_auto_req_mode 0.940s 53.915us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.990s 1276.058us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 18.216us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.100s 19.686us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.630s 367.831us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.630s 367.831us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 41.921us 1 1 100.00
edn_csr_rw 0.760s 42.411us 1 1 100.00
edn_csr_aliasing 1.050s 248.731us 1 1 100.00
edn_same_csr_outstanding 1.170s 30.916us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 41.921us 1 1 100.00
edn_csr_rw 0.760s 42.411us 1 1 100.00
edn_csr_aliasing 1.050s 248.731us 1 1 100.00
edn_same_csr_outstanding 1.170s 30.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.970s 1051.766us 1 1 100.00
edn_tl_intg_err 1.890s 127.937us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.880s 20.120us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.160s 164.121us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.970s 1051.766us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.970s 1051.766us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.970s 1051.766us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.970s 1051.766us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.160s 164.121us 1 1 100.00
edn_sec_cm 6.970s 1051.766us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.160s 164.121us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.890s 127.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 41.640s 9797.523us 1 1 100.00