Simulation Results: edn/edn1

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.88 %
  • code
  • 83.42 %
  • assert
  • 98.44 %
  • func
  • 78.78 %
  • line
  • 97.88 %
  • branch
  • 92.42 %
  • cond
  • 89.00 %
  • toggle
  • 95.76 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.730s 128.856us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.720s 19.876us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 14.635us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.390s 278.095us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.250s 159.165us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.900s 58.371us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 14.635us 1 1 100.00
edn_csr_aliasing 1.250s 159.165us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.180s 60.083us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.180s 60.083us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.180s 60.083us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.810s 40.896us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 31.662us 1 1 100.00
errs 1 1 100.00
edn_err 1.180s 27.041us 1 1 100.00
disable 1 2 50.00
edn_disable 0.770s 13.970us 1 1 100.00
edn_disable_auto_req_mode 1.010s 18.869us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.330s 2454.931us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.920s 19.802us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.700s 38.247us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.750s 233.312us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.750s 233.312us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.720s 19.876us 1 1 100.00
edn_csr_rw 0.770s 14.635us 1 1 100.00
edn_csr_aliasing 1.250s 159.165us 1 1 100.00
edn_same_csr_outstanding 1.150s 75.276us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.720s 19.876us 1 1 100.00
edn_csr_rw 0.770s 14.635us 1 1 100.00
edn_csr_aliasing 1.250s 159.165us 1 1 100.00
edn_same_csr_outstanding 1.150s 75.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.480s 2007.156us 1 1 100.00
edn_tl_intg_err 1.490s 250.064us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 18.477us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 31.662us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.480s 2007.156us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.480s 2007.156us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.480s 2007.156us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.480s 2007.156us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 31.662us 1 1 100.00
edn_sec_cm 2.480s 2007.156us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 31.662us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.490s 250.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 22.830s 4788.207us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 102766513160115110078189787418134184422710132517483343977050518479391433799749 88
UVM_INFO @ 18869035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---