Simulation Results: flash_ctrl

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.69 %
  • code
  • 94.23 %
  • assert
  • 97.02 %
  • func
  • 95.82 %
  • line
  • 95.96 %
  • branch
  • 97.16 %
  • cond
  • 93.89 %
  • toggle
  • 97.73 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 26.980s 18.230us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 15.060s 17.992us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.910s 285.478us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.830s 23.951us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 34.180s 3664.513us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 18.500s 217.311us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 10.900s 233.385us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.830s 23.951us 1 1 100.00
flash_ctrl_csr_aliasing 18.500s 217.311us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.600s 36.679us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 7.230s 60.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.930s 34.281us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 62.880s 140.807us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1223.600s 608123.205us 1 1 100.00
flash_ctrl_hw_rma_reset 497.400s 160184.603us 1 1 100.00
flash_ctrl_lcmgr_intg 6.260s 64.171us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1082.960s 518410.913us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 198.250s 9788.551us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 8.020s 56.136us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2489.080s 108369.178us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 42.220s 469.897us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.650s 32.911us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.530s 32.876us 1 1 100.00
flash_ctrl_re_evict 17.870s 237.060us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 28.750s 105.680us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 28.750s 105.680us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 228.010s 30079.271us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 16.530s 2279.375us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 288.310s 1156.172us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 313.210s 7008.923us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 305.340s 716.563us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 928.030s 1150.296us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.240s 24.635us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 140.620s 7191.746us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.630s 54.264us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.830s 27.832us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 48.430s 49.431us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 86.620s 4692.667us 1 1 100.00
flash_ctrl_otp_reset 62.960s 329.578us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1223.600s 608123.205us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 134.240s 2182.733us 1 1 100.00
flash_ctrl_intr_wr 49.590s 5211.435us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 74.240s 12545.652us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 111.720s 44244.118us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 41.660s 8959.456us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.280s 1885.148us 1 1 100.00
double_bit_err 4 5 80.00
flash_ctrl_read_word_sweep_derr 10.420s 112.361us 1 1 100.00
flash_ctrl_ro_derr 93.550s 1983.095us 0 1 0.00
flash_ctrl_rw_derr 122.890s 1405.474us 1 1 100.00
flash_ctrl_derr_detect 99.790s 768.108us 1 1 100.00
flash_ctrl_integrity 365.360s 23271.628us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.840s 56.686us 1 1 100.00
flash_ctrl_ro_serr 113.410s 936.557us 1 1 100.00
flash_ctrl_rw_serr 101.380s 5606.757us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 42.700s 2180.839us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 43.290s 1695.717us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 101.990s 5383.628us 1 1 100.00
flash_ctrl_write_word_sweep 7.890s 80.253us 1 1 100.00
flash_ctrl_read_word_sweep 6.620s 102.853us 1 1 100.00
flash_ctrl_ro 81.690s 5665.235us 1 1 100.00
flash_ctrl_rw 392.590s 9351.673us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 18.970s 346.304us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 574.870s 80747.885us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 48.280s 10033.362us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.050s 60.987us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.070s 29.909us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 12.880s 113.343us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 12.880s 113.343us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.910s 285.478us 1 1 100.00
flash_ctrl_csr_rw 7.830s 23.951us 1 1 100.00
flash_ctrl_csr_aliasing 18.500s 217.311us 1 1 100.00
flash_ctrl_same_csr_outstanding 17.310s 669.860us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.910s 285.478us 1 1 100.00
flash_ctrl_csr_rw 7.830s 23.951us 1 1 100.00
flash_ctrl_csr_aliasing 18.500s 217.311us 1 1 100.00
flash_ctrl_same_csr_outstanding 17.310s 669.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.520s 133.861us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 27.520s 133.861us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 27.520s 133.861us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 27.520s 133.861us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 25.630s 193.069us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1789.370s 1559.359us 1 1 100.00
flash_ctrl_tl_intg_err 211.490s 1669.373us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 211.490s 1669.373us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 211.490s 1669.373us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.470s 72.902us 1 1 100.00
flash_ctrl_wr_intg 6.930s 50.445us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 26.980s 18.230us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 62.960s 329.578us 1 1 100.00
flash_ctrl_disable 10.630s 54.264us 1 1 100.00
flash_ctrl_sec_info_access 49.700s 14730.076us 1 1 100.00
flash_ctrl_connect 7.830s 27.832us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.140s 24.139us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.830s 23.951us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.520s 133.861us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.830s 23.951us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.520s 133.861us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.830s 23.951us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 27.520s 133.861us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.630s 54.264us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.470s 72.902us 1 1 100.00
flash_ctrl_access_after_disable 7.430s 50.387us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.400s 66.376us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.630s 54.264us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 16.530s 2279.375us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 392.590s 9351.673us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 101.380s 5606.757us 1 1 100.00
flash_ctrl_rw_derr 122.890s 1405.474us 1 1 100.00
flash_ctrl_integrity 365.360s 23271.628us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1223.600s 608123.205us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1789.370s 1559.359us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1789.370s 1559.359us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1789.370s 1559.359us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1789.370s 1559.359us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 12.190s 870.931us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.350s 30.350us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 8.200s 44.139us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1789.370s 1559.359us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1789.370s 1559.359us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1789.370s 1559.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.090s 70.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 428.600s 8122.874us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 1 test run
flash_ctrl_ro_derr 74339752101447698351118397299523894981813613215091615511180768394086726589600 108
UVM_INFO @ 1983095.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---