Simulation Results: hmac

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.69 %
  • code
  • 97.40 %
  • assert
  • 97.60 %
  • func
  • 44.07 %
  • line
  • 99.54 %
  • branch
  • 98.51 %
  • cond
  • 95.06 %
  • toggle
  • 99.77 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.170s 148.429us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.770s 155.955us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.750s 192.870us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 13.100s 38993.908us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.770s 470.816us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.190s 240.402us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.750s 192.870us 1 1 100.00
hmac_csr_aliasing 3.770s 470.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 31.630s 2862.967us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 17.690s 589.369us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.050s 441.533us 1 1 100.00
hmac_test_sha384_vectors 20.580s 2351.703us 1 1 100.00
hmac_test_sha512_vectors 19.480s 323.070us 1 1 100.00
hmac_test_hmac256_vectors 9.790s 841.517us 1 1 100.00
hmac_test_hmac384_vectors 7.650s 628.518us 1 1 100.00
hmac_test_hmac512_vectors 12.630s 874.920us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.090s 1409.241us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 331.100s 3970.696us 1 1 100.00
error 1 1 100.00
hmac_error 12.480s 19830.835us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 72.500s 2679.598us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.170s 148.429us 1 1 100.00
hmac_long_msg 31.630s 2862.967us 1 1 100.00
hmac_back_pressure 17.690s 589.369us 1 1 100.00
hmac_datapath_stress 331.100s 3970.696us 1 1 100.00
hmac_burst_wr 6.090s 1409.241us 1 1 100.00
hmac_stress_all 2569.800s 188517.358us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.170s 148.429us 1 1 100.00
hmac_long_msg 31.630s 2862.967us 1 1 100.00
hmac_back_pressure 17.690s 589.369us 1 1 100.00
hmac_datapath_stress 331.100s 3970.696us 1 1 100.00
hmac_wipe_secret 72.500s 2679.598us 1 1 100.00
hmac_test_sha256_vectors 8.050s 441.533us 1 1 100.00
hmac_test_sha384_vectors 20.580s 2351.703us 1 1 100.00
hmac_test_sha512_vectors 19.480s 323.070us 1 1 100.00
hmac_test_hmac256_vectors 9.790s 841.517us 1 1 100.00
hmac_test_hmac384_vectors 7.650s 628.518us 1 1 100.00
hmac_test_hmac512_vectors 12.630s 874.920us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.170s 148.429us 1 1 100.00
hmac_long_msg 31.630s 2862.967us 1 1 100.00
hmac_back_pressure 17.690s 589.369us 1 1 100.00
hmac_datapath_stress 331.100s 3970.696us 1 1 100.00
hmac_burst_wr 6.090s 1409.241us 1 1 100.00
hmac_error 12.480s 19830.835us 1 1 100.00
hmac_wipe_secret 72.500s 2679.598us 1 1 100.00
hmac_test_sha256_vectors 8.050s 441.533us 1 1 100.00
hmac_test_sha384_vectors 20.580s 2351.703us 1 1 100.00
hmac_test_sha512_vectors 19.480s 323.070us 1 1 100.00
hmac_test_hmac256_vectors 9.790s 841.517us 1 1 100.00
hmac_test_hmac384_vectors 7.650s 628.518us 1 1 100.00
hmac_test_hmac512_vectors 12.630s 874.920us 1 1 100.00
hmac_stress_all 2569.800s 188517.358us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 2569.800s 188517.358us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.720s 47.774us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.620s 19.602us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.500s 234.466us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.500s 234.466us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.770s 155.955us 1 1 100.00
hmac_csr_rw 0.750s 192.870us 1 1 100.00
hmac_csr_aliasing 3.770s 470.816us 1 1 100.00
hmac_same_csr_outstanding 2.010s 756.433us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.770s 155.955us 1 1 100.00
hmac_csr_rw 0.750s 192.870us 1 1 100.00
hmac_csr_aliasing 3.770s 470.816us 1 1 100.00
hmac_same_csr_outstanding 2.010s 756.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.060s 69.605us 1 1 100.00
hmac_tl_intg_err 1.500s 80.870us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.500s 80.870us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.170s 148.429us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.250s 495.450us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 35.840s 1743.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.880s 592.093us 1 1 100.00