Simulation Results

Simulation Results: i2c

02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.06 %

code
81.59 %

assert
97.25 %

func
82.35 %

line
96.51 %

branch
92.48 %

cond
84.67 %

toggle
89.66 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	45.920s	4271.869us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.630s	3636.936us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.800s	120.239us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.820s	93.331us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.440s	317.453us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.670s	400.407us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.810s	24.842us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.820s	93.331us	1	1	100.00
	i2c_csr_aliasing	1.670s	400.407us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.360s	340.020us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	123.020s	9360.649us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	411.180s	26200.276us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.680s	33.694us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	63.930s	4763.665us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	41.750s	16805.262us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.850s	114.306us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.490s	1807.084us	1	1	100.00
	i2c_host_fifo_reset_rx	2.190s	253.274us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	30.590s	8294.914us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	24.480s	3162.479us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	3.330s	156.487us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.600s	381.041us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	46.590s	33148.571us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.080s	617.884us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	16.220s	6469.617us	1	1	100.00
	i2c_target_intr_smoke	3.360s	6286.251us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.990s	160.048us	1	1	100.00
	i2c_target_fifo_reset_tx	0.860s	358.658us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	487.180s	46668.747us	1	1	100.00
	i2c_target_stress_rd	16.220s	6469.617us	1	1	100.00
	i2c_target_intr_stress_wr	159.790s	17810.425us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	3.930s	1223.072us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.400s	1666.743us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.990s	2270.229us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.130s	426.170us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.720s	461.164us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.070s	425.962us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	411.180s	26200.276us	1	1	100.00
	i2c_host_perf_precise	5.040s	570.650us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	24.480s	3162.479us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	2.980s	175.897us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.290s	2128.963us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.480s	556.623us	1	1	100.00
	i2c_target_nack_txstretch	1.410s	145.344us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.230s	1008.407us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.530s	423.304us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.730s	50.708us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.720s	52.435us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.570s	324.277us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.570s	324.277us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.800s	120.239us	1	1	100.00
	i2c_csr_rw	0.820s	93.331us	1	1	100.00
	i2c_csr_aliasing	1.670s	400.407us	1	1	100.00
	i2c_same_csr_outstanding	1.020s	26.183us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.800s	120.239us	1	1	100.00
	i2c_csr_rw	0.820s	93.331us	1	1	100.00
	i2c_csr_aliasing	1.670s	400.407us	1	1	100.00
	i2c_same_csr_outstanding	1.020s	26.183us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.170s	142.014us	1	1	100.00
	i2c_sec_cm	1.080s	471.030us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.170s	142.014us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	23.650s	867.547us	1
target_error_intr				1
	i2c_target_unexp_stop	0.970s	157.311us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	3.030s	1609.043us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	88563564460485834281912405855848007188931989616495039083832577985665641840948	136	UVM_INFO @ 340020326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	8303011238792417373842528851932246373194006440427335834842877070851977463392	136	UVM_INFO @ 9360648750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	102949254270371088324216603024526695360831997667750185579819605666464096541264	101	UVM_INFO @ 867547439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	53556558631338800534537789301982017947835142060204044876401250230266015696171	84	UVM_INFO @ 1609042895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	112098751669560883070048247414530279761202376408441382061434886521747901197666	84	UVM_INFO @ 381041052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	92252054673532982854183927406833084678187949290205250330058154320428394950626	78	UVM_INFO @ 157311461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	102067147597101447554036731563261922543717642737738760920459596110957409274077	85	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @70403