Simulation Results: lc_ctrl/volatile_unlock_disabled

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.44 %
  • code
  • 83.75 %
  • assert
  • 94.69 %
  • func
  • 92.88 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 79.15 %
  • toggle
  • 86.77 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.660s 30.733us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.790s 25.595us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 40.588us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 63.466us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.790s 20.151us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.330s 21.991us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 40.588us 1 1 100.00
lc_ctrl_csr_aliasing 1.790s 20.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.960s 218.186us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.110s 389.019us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.140s 14.501us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.250s 211.220us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.430s 1058.350us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_ctrl_prog_failure 2.250s 211.220us 1 1 100.00
lc_ctrl_errors 6.430s 1058.350us 1 1 100.00
lc_ctrl_security_escalation 3.500s 200.975us 1 1 100.00
lc_ctrl_jtag_state_failure 25.610s 4451.129us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.440s 291.697us 1 1 100.00
lc_ctrl_jtag_errors 31.680s 14940.727us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.870s 290.540us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.900s 456.326us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.440s 291.697us 1 1 100.00
lc_ctrl_jtag_errors 31.680s 14940.727us 1 1 100.00
lc_ctrl_jtag_access 4.320s 1762.676us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.200s 2982.273us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.990s 2298.861us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.640s 182.170us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.590s 934.048us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.970s 698.664us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.170s 166.485us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.910s 64.018us 1 1 100.00
lc_ctrl_jtag_alert_test 1.280s 25.077us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.050s 1140.775us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.850s 25.101us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 31.240s 2976.392us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.300s 148.483us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.180s 165.681us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.180s 165.681us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 25.595us 1 1 100.00
lc_ctrl_csr_rw 0.830s 40.588us 1 1 100.00
lc_ctrl_csr_aliasing 1.790s 20.151us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.590s 183.231us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 25.595us 1 1 100.00
lc_ctrl_csr_rw 0.830s 40.588us 1 1 100.00
lc_ctrl_csr_aliasing 1.790s 20.151us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.590s 183.231us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.420s 306.606us 1 1 100.00
lc_ctrl_tl_intg_err 2.360s 80.693us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.360s 80.693us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.110s 389.019us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_ctrl_sec_cm 5.420s 306.606us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_ctrl_sec_cm 5.420s 306.606us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_ctrl_sec_cm 5.420s 306.606us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_ctrl_sec_cm 5.420s 306.606us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_ctrl_sec_cm 5.420s 306.606us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_ctrl_sec_cm 5.420s 306.606us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_ctrl_sec_cm 5.420s 306.606us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.800s 401.418us 1 1 100.00
lc_ctrl_sec_cm 5.420s 306.606us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.500s 200.975us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.960s 218.186us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.900s 456.326us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.080s 1381.506us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.080s 1381.506us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 10.340s 3680.747us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.260s 346.706us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.260s 346.706us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 46.200s 8536.782us 1 1 100.00