Simulation Results: lc_ctrl/volatile_unlock_enabled

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.58 %
  • code
  • 83.79 %
  • assert
  • 93.85 %
  • func
  • 91.10 %
  • line
  • 97.22 %
  • branch
  • 93.66 %
  • cond
  • 79.06 %
  • toggle
  • 86.40 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.350s 157.244us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.850s 76.716us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 25.142us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.570s 532.466us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 31.337us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.010s 59.673us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 25.142us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 31.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.990s 92.026us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.760s 295.316us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.180s 13.326us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.970s 557.724us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.520s 1164.035us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_ctrl_prog_failure 1.970s 557.724us 1 1 100.00
lc_ctrl_errors 5.520s 1164.035us 1 1 100.00
lc_ctrl_security_escalation 10.840s 1852.451us 1 1 100.00
lc_ctrl_jtag_state_failure 17.030s 3931.533us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.260s 887.193us 1 1 100.00
lc_ctrl_jtag_errors 10.620s 1055.706us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 11.630s 627.948us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.820s 1958.875us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.260s 887.193us 1 1 100.00
lc_ctrl_jtag_errors 10.620s 1055.706us 1 1 100.00
lc_ctrl_jtag_access 1.240s 72.040us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.870s 1991.680us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.510s 261.033us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.910s 80.792us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.950s 6366.299us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.080s 436.417us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.260s 22.709us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.500s 101.382us 1 1 100.00
lc_ctrl_jtag_alert_test 1.020s 40.195us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.820s 483.446us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.100s 13.955us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 48.450s 24943.086us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.180s 53.333us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.910s 148.911us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.910s 148.911us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 76.716us 1 1 100.00
lc_ctrl_csr_rw 0.920s 25.142us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 31.337us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 34.545us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 76.716us 1 1 100.00
lc_ctrl_csr_rw 0.920s 25.142us 1 1 100.00
lc_ctrl_csr_aliasing 1.140s 31.337us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.200s 34.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.570s 132.792us 1 1 100.00
lc_ctrl_tl_intg_err 2.160s 152.787us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.160s 152.787us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.760s 295.316us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_ctrl_sec_cm 5.570s 132.792us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_ctrl_sec_cm 5.570s 132.792us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_ctrl_sec_cm 5.570s 132.792us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_ctrl_sec_cm 5.570s 132.792us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_ctrl_sec_cm 5.570s 132.792us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_ctrl_sec_cm 5.570s 132.792us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_ctrl_sec_cm 5.570s 132.792us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.760s 279.976us 1 1 100.00
lc_ctrl_sec_cm 5.570s 132.792us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 10.840s 1852.451us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.990s 92.026us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.820s 1958.875us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.600s 1943.908us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.600s 1943.908us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.290s 906.941us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.140s 1934.177us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.140s 1934.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 37.830s 7559.993us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 79411222594836093709530401688362372233277079251739415290449399699657926017119 1460
UVM_INFO @ 7559993346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---