Simulation Results: otbn

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.45 %
  • code
  • 80.93 %
  • assert
  • 87.78 %
  • func
  • 93.64 %
  • block
  • 97.70 %
  • line
  • 97.88 %
  • branch
  • 81.86 %
  • toggle
  • 80.61 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 138.453us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 22.335us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 25.000s 15.500us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 24.000s 30.127us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 27.000s 168.481us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 28.000s 30.904us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 26.000s 72.670us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 24.000s 30.127us 1 1 100.00
otbn_csr_aliasing 28.000s 30.904us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 115.000s 29653.813us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 47.000s 4534.197us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 34.000s 1022.119us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 56.000s 821.553us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 189.000s 6425.908us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 48.000s 278.229us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 27.000s 52.079us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 25.852us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 69.596us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 28.000s 69.067us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 16.000s 15.782us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 91.271us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 91.271us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 25.000s 15.500us 1 1 100.00
otbn_csr_rw 24.000s 30.127us 1 1 100.00
otbn_csr_aliasing 28.000s 30.904us 1 1 100.00
otbn_same_csr_outstanding 4.000s 37.541us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 25.000s 15.500us 1 1 100.00
otbn_csr_rw 24.000s 30.127us 1 1 100.00
otbn_csr_aliasing 28.000s 30.904us 1 1 100.00
otbn_same_csr_outstanding 4.000s 37.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 21.000s 21.991us 1 1 100.00
otbn_dmem_err 28.000s 27.932us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 31.000s 30.450us 1 1 100.00
otbn_controller_ispr_rdata_err 30.000s 54.049us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 25.797us 0 1 0.00
otbn_urnd_err 8.000s 37.088us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 22.000s 79.992us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 91.595us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 26.021us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
otbn_tl_intg_err 11.000s 242.276us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 24.000s 398.461us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 138.453us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 28.000s 27.932us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 21.000s 21.991us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 11.000s 242.276us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 27.000s 52.079us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 21.000s 21.991us 1 1 100.00
otbn_dmem_err 28.000s 27.932us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 25.852us 1 1 100.00
otbn_illegal_mem_acc 22.000s 79.992us 1 1 100.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 22.335us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 21.000s 21.991us 1 1 100.00
otbn_dmem_err 28.000s 27.932us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 25.852us 1 1 100.00
otbn_illegal_mem_acc 22.000s 79.992us 1 1 100.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 27.000s 52.079us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 21.000s 21.991us 1 1 100.00
otbn_dmem_err 28.000s 27.932us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 25.852us 1 1 100.00
otbn_illegal_mem_acc 22.000s 79.992us 1 1 100.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 22.335us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 24.000s 15.710us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 108.427us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 48.000s 446.722us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 48.000s 446.722us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 63.945us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 424.129us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 15.574us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 7.000s 15.574us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 17.000s 49.240us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 22.335us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 22.335us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 22.335us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 189.000s 6425.908us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 22.335us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 22.335us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 10.000s 139.205us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 22.335us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 3.000s 2.397us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 11.000s 65.018us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 22.600us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_mac_bignum_acc_err 87807187589451797176942150023860965967471254327846048207412854087173098350146 124
UVM_INFO @ 25797222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 14614818237104897808632472124594876720392126015382294547269226673385609661503 159
UVM_INFO @ 65017503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 74128494417964805406771493521341575821826268041451935351296045248914741248467 85
UVM_ERROR @ 2397172 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2397172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---