Simulation Results: pwrmgr

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.89 %
  • code
  • 91.22 %
  • assert
  • 98.43 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.47 %
  • toggle
  • 91.15 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.680s 34.758us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.700s 24.718us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.730s 25.302us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.670s 772.685us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.790s 32.211us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.820s 105.714us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.730s 25.302us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 32.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.840s 274.556us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.840s 274.556us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.670s 26.235us 1 1 100.00
pwrmgr_lowpower_invalid 0.640s 55.975us 1 1 100.00
reset 0 2 0.00
pwrmgr_reset 0.610s 50.399us 0 1 0.00
pwrmgr_reset_invalid 0.710s 57.749us 0 1 0.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 0.610s 50.399us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.050s 281.470us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.940s 206.857us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.760s 56.156us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.290s 3193.364us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.650s 19.372us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.260s 134.295us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.260s 134.295us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.700s 24.718us 1 1 100.00
pwrmgr_csr_rw 0.730s 25.302us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 32.211us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 39.215us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.700s 24.718us 1 1 100.00
pwrmgr_csr_rw 0.730s 25.302us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 32.211us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 39.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.950s 1018.824us 1 1 100.00
pwrmgr_sec_cm 1.250s 953.417us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.250s 953.417us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.250s 953.417us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.950s 1018.824us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.470s 1162.444us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.050s 281.470us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.970s 815.154us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.790s 50.213us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.600s 34.099us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.250s 953.417us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.250s 953.417us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.250s 953.417us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.560s 69.070us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.550s 71.970us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.720s 121.992us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 25.302us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.730s 25.302us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.690s 361.421us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 13.630s 6129.123us 1 1 100.00

Error Messages

   Test seed line log context
Offending 'pwr_rst_o.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx]' 1 test run
pwrmgr_reset 103546907349664083645118944372752646474217964874616497432783864019244291316211 92
UVM_ERROR @ 50398506 ps: (pwrmgr_sec_cm_checker_assert.sv:208) [ASSERT FAILED] RstreqChkMainpd_A
UVM_INFO @ 50398506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitEnableClocks 1 test run
pwrmgr_reset_invalid 114895685694152592206076188841067838223315738562423415968484177695390952486574 94
UVM_INFO @ 57748643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---