Simulation Results: rom_ctrl/64kb

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.14 %
  • code
  • 95.58 %
  • assert
  • 96.66 %
  • func
  • 96.18 %
  • line
  • 99.19 %
  • branch
  • 98.91 %
  • cond
  • 98.22 %
  • toggle
  • 94.93 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.390s 1159.749us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.970s 800.463us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.460s 286.448us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.320s 1073.255us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 1114.766us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 9.190s 288.233us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.460s 286.448us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 1114.766us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.610s 305.881us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.990s 212.437us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.710s 688.623us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 27.230s 987.068us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.350s 380.403us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.470s 294.924us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.840s 298.448us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.840s 298.448us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.970s 800.463us 1 1 100.00
rom_ctrl_csr_rw 7.460s 286.448us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 1114.766us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.020s 1068.707us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.970s 800.463us 1 1 100.00
rom_ctrl_csr_rw 7.460s 286.448us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 1114.766us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.020s 1068.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.490s 2896.843us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 468.090s 1754.330us 1 1 100.00
rom_ctrl_tl_intg_err 54.540s 285.123us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 468.090s 1754.330us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 468.090s 1754.330us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 468.090s 1754.330us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 468.090s 1754.330us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.390s 1159.749us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.390s 1159.749us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.390s 1159.749us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 54.540s 285.123us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
rom_ctrl_kmac_err_chk 13.350s 380.403us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 76.880s 1569.354us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.490s 2896.843us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 468.090s 1754.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 81.090s 3877.458us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 38233775355766005953868264958745969434346346799689562521547874097900603167216 79
UVM_INFO @ 688622634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---