Simulation Results: rstmgr

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.31 %
  • code
  • 99.15 %
  • assert
  • 98.53 %
  • func
  • 97.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 97.85 %
  • toggle
  • 99.41 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.090s 138.901us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.280s 154.083us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.920s 67.063us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.960s 382.075us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.470s 242.451us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.030s 143.120us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.920s 67.063us 1 1 100.00
rstmgr_csr_aliasing 1.470s 242.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.940s 227.238us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.110s 537.447us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.070s 101.158us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.290s 1505.050us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.290s 1505.050us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.290s 1505.050us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.290s 1505.050us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 25.300s 11728.198us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.920s 67.154us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.680s 301.707us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.680s 301.707us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.280s 154.083us 1 1 100.00
rstmgr_csr_rw 0.920s 67.063us 1 1 100.00
rstmgr_csr_aliasing 1.470s 242.451us 1 1 100.00
rstmgr_same_csr_outstanding 1.480s 316.781us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.280s 154.083us 1 1 100.00
rstmgr_csr_rw 0.920s 67.063us 1 1 100.00
rstmgr_csr_aliasing 1.470s 242.451us 1 1 100.00
rstmgr_same_csr_outstanding 1.480s 316.781us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 13.020s 8440.676us 1 1 100.00
rstmgr_tl_intg_err 1.720s 517.203us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 13.020s 8440.676us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 13.020s 8440.676us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.720s 517.203us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.150s 192.029us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.760s 1397.794us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.050s 302.784us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 13.020s 8440.676us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 67.063us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 67.063us 1 1 100.00