Simulation Results: rv_timer

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 96.47 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.900s 765.576us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.630s 17.380us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.710s 27.241us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.380s 197.453us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.720s 19.093us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.760s 20.173us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.710s 27.241us 1 1 100.00
rv_timer_csr_aliasing 0.720s 19.093us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.920s 661.979us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.890s 1697.055us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 92.870s 99713.664us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 92.870s 99713.664us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.530s 5036.527us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 46.230us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 13.214us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.350s 449.413us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.350s 449.413us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 17.380us 1 1 100.00
rv_timer_csr_rw 0.710s 27.241us 1 1 100.00
rv_timer_csr_aliasing 0.720s 19.093us 1 1 100.00
rv_timer_same_csr_outstanding 0.750s 37.998us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 17.380us 1 1 100.00
rv_timer_csr_rw 0.710s 27.241us 1 1 100.00
rv_timer_csr_aliasing 0.720s 19.093us 1 1 100.00
rv_timer_same_csr_outstanding 0.750s 37.998us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.800s 72.488us 1 1 100.00
rv_timer_tl_intg_err 0.760s 354.085us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.760s 354.085us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 2.330s 1886.042us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.720s 45.561us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 11.860s 15643.996us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 2888583108728445677352460633686232041396539934158025064384962484594788016426 78
UVM_INFO @ 1886041595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 2250334823636315352302616764815279395701820207840887228190258216273752051838 75
UVM_INFO @ 45561348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---