Simulation Results: spi_host

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.82 %
  • code
  • 91.30 %
  • assert
  • 95.09 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 26.000s 1056.171us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 18.512us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 53.775us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 815.707us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 52.933us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 77.392us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 53.775us 1 1 100.00
spi_host_csr_aliasing 2.000s 52.933us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 19.659us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 50.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 83.090us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 181.669us 1 1 100.00
spi_host_error_cmd 1.000s 19.770us 1 1 100.00
spi_host_event 4.000s 232.692us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 73.386us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 73.386us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 73.386us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 121.000s 15347.989us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 118.432us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 63.887us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 73.386us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 73.386us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 26.000s 1056.171us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 26.000s 1056.171us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 52.000s 4190.662us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 963.872us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 28.000s 1199.815us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 7.000s 4192.724us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 181.669us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 19.121us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 132.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 80.531us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 80.531us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.512us 1 1 100.00
spi_host_csr_rw 1.000s 53.775us 1 1 100.00
spi_host_csr_aliasing 2.000s 52.933us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 25.218us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.512us 1 1 100.00
spi_host_csr_rw 1.000s 53.775us 1 1 100.00
spi_host_csr_aliasing 2.000s 52.933us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 25.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 236.736us 1 1 100.00
spi_host_sec_cm 2.000s 133.594us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 236.736us 1 1 100.00