Simulation Results: sram_ctrl/main

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.92 %
  • code
  • 95.67 %
  • assert
  • 98.10 %
  • func
  • 94.00 %
  • block
  • 96.03 %
  • line
  • 96.83 %
  • branch
  • 94.01 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 11128.666us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 46.613us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 42.164us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 222.441us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.957us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 7132.216us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 42.164us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.957us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 91.000s 6435.759us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 41.000s 990.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 6904.902us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 131.000s 3851.877us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 120.000s 7364.194us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 39.000s 35910.678us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 29.000s 51806.595us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 35.000s 92705.751us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1523.196us 1 1 100.00
sram_ctrl_partial_access_b2b 147.000s 52867.405us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 5.000s 2748.925us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 1347.022us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 2663.177us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 3586.807us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 3733.275us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 184.000s 109905.086us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 16.444us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 265.549us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 265.549us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 46.613us 1 1 100.00
sram_ctrl_csr_rw 1.000s 42.164us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.957us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 48.353us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 46.613us 1 1 100.00
sram_ctrl_csr_rw 1.000s 42.164us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 24.957us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 48.353us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 15.000s 3876.352us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 726.979us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 488.834us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 726.979us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 488.834us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 3586.807us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 3586.807us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 42.164us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 35.000s 92705.751us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 35.000s 92705.751us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 35.000s 92705.751us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 29.000s 51806.595us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 2655.816us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 15.000s 3876.352us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 1301.356us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 11128.666us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 11128.666us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 35.000s 92705.751us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 726.979us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 29.000s 51806.595us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 726.979us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 726.979us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 11128.666us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 726.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.000s 4483.092us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 70606618538302838396699679270548276359436656554910904239041022592540110162373 86
UVM_INFO @ 2748925371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 103876404806429356797832306056016208613141712453877790840632850563998528139694 86
UVM_INFO @ 1347021664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 81769234298077215851929183000789157008639370835244417287588708117727541325854 86
UVM_INFO @ 2663176761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---