Simulation Results: sram_ctrl/ret

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.71 %
  • code
  • 82.06 %
  • assert
  • 98.08 %
  • func
  • 95.00 %
  • block
  • 93.49 %
  • line
  • 94.61 %
  • branch
  • 88.89 %
  • toggle
  • 78.07 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 47.999us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 46.021us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 30.091us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 226.746us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 284.549us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 30.091us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.000us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 3535.231us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 175.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 4.000s 426.345us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 62.000s 2451.597us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 2310.949us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 16.000s 682.703us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 2638.452us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 2303.069us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 84.361us 1 1 100.00
sram_ctrl_partial_access_b2b 198.000s 96424.018us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 102.937us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 157.975us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 34.822us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 486.604us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 86.135us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 17.000s 671.409us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 20.388us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 324.266us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 324.266us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 46.021us 1 1 100.00
sram_ctrl_csr_rw 2.000s 30.091us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.768us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 46.021us 1 1 100.00
sram_ctrl_csr_rw 2.000s 30.091us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.000us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 29.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1510.540us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 745.815us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 279.333us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 745.815us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 279.333us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 486.604us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 486.604us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 30.091us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 2303.069us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 2303.069us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 2303.069us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 2638.452us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 50.268us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 1510.540us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 130.186us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 47.999us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 47.999us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 2303.069us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 745.815us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 2638.452us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 745.815us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 745.815us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 47.999us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 745.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 22.000s 1200.799us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 80231759202034796773368423316985856841626632500006384142518850684415733294755 86
UVM_INFO @ 102937272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 12163131096050116645543103302080789112333195183729026369249772150391897825529 86
UVM_INFO @ 157975429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 15761109394894837119321382082347415414833447400237546096265369915333986660441 86
UVM_INFO @ 34821517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---