Simulation Results: sysrst_ctrl

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.85 %
  • code
  • 87.25 %
  • assert
  • 85.63 %
  • func
  • 72.67 %
  • line
  • 94.08 %
  • branch
  • 95.29 %
  • cond
  • 91.99 %
  • toggle
  • 99.77 %
  • FSM
  • 55.13 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.140s 2109.994us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.610s 2500.854us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.310s 2241.060us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.750s 2374.497us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.540s 4027.420us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.170s 2146.111us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 50.950s 76463.618us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.870s 2589.848us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.610s 2046.690us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.170s 2146.111us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.870s 2589.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 28.610s 82444.360us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 151.890s 93898.166us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.110s 3115.624us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.340s 2863.280us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.650s 2517.920us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.520s 2221.767us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.360s 3021.218us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.630s 2616.216us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.710s 5887.666us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 41.450s 35099.211us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 3.150s 7072.266us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.180s 2023.817us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.200s 2021.241us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.760s 2591.145us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.760s 2591.145us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.540s 4027.420us 1 1 100.00
sysrst_ctrl_csr_rw 1.170s 2146.111us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.870s 2589.848us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.300s 5633.293us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.540s 4027.420us 1 1 100.00
sysrst_ctrl_csr_rw 1.170s 2146.111us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.870s 2589.848us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 8.300s 5633.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 27.890s 22015.553us 1 1 100.00
sysrst_ctrl_tl_intg_err 54.610s 42441.267us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 54.610s 42441.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.170s 5190.081us 1 1 100.00