Simulation Results: uart

 
02/07/2026 15:30:32 DVSim: v1.49.12 sha: f99e229 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.02 %
  • code
  • 91.62 %
  • assert
  • 97.12 %
  • func
  • 54.31 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.57 %
  • toggle
  • 74.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.330s 304.139us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.590s 16.391us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.570s 43.264us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.980s 635.117us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.820s 82.783us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.700s 20.672us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.570s 43.264us 1 1 100.00
uart_csr_aliasing 0.820s 82.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 3.230s 2823.698us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.330s 304.139us 1 1 100.00
uart_tx_rx 3.230s 2823.698us 1 1 100.00
parity_error 2 2 100.00
uart_intr 6.270s 25787.423us 1 1 100.00
uart_rx_parity_err 11.270s 42167.426us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 3.230s 2823.698us 1 1 100.00
uart_intr 6.270s 25787.423us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 53.740s 123328.170us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 29.550s 130393.380us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 19.140s 92441.912us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 6.270s 25787.423us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 6.270s 25787.423us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 6.270s 25787.423us 1 1 100.00
perf 1 1 100.00
uart_perf 162.020s 12081.991us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.720s 9499.310us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.720s 9499.310us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 6.860s 21675.096us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.920s 4307.179us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.690s 1188.878us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 24.680s 5352.473us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 87.280s 72875.627us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 113.400s 137754.479us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.610s 14.103us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 12.530us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.880s 585.642us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.880s 585.642us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.590s 16.391us 1 1 100.00
uart_csr_rw 0.570s 43.264us 1 1 100.00
uart_csr_aliasing 0.820s 82.783us 1 1 100.00
uart_same_csr_outstanding 0.640s 76.489us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.590s 16.391us 1 1 100.00
uart_csr_rw 0.570s 43.264us 1 1 100.00
uart_csr_aliasing 0.820s 82.783us 1 1 100.00
uart_same_csr_outstanding 0.640s 76.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.780s 158.595us 1 1 100.00
uart_tl_intg_err 1.220s 251.809us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.220s 251.809us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 29.240s 3775.711us 1 1 100.00