Simulation Results: adc_ctrl

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.89 %
  • code
  • 92.78 %
  • assert
  • 91.90 %
  • func
  • 12.99 %
  • line
  • 98.13 %
  • branch
  • 96.41 %
  • cond
  • 86.27 %
  • toggle
  • 99.29 %
  • FSM
  • 83.78 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.340s 5745.453us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.100s 1385.030us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.020s 497.988us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 18.330s 26222.017us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.720s 836.908us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.440s 575.273us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.020s 497.988us 1 1 100.00
adc_ctrl_csr_aliasing 1.720s 836.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.740s 324.502us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.690s 352.829us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.920s 497.270us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.880s 466.718us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.020s 317.587us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.860s 440.067us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.400s 498.601us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.910s 299.618us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 7.520s 5164.470us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 46.890s 32086.593us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 170.220s 118614.990us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.790s 753.719us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.090s 299.246us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.820s 520.362us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.740s 535.281us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.740s 535.281us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.100s 1385.030us 1 1 100.00
adc_ctrl_csr_rw 1.020s 497.988us 1 1 100.00
adc_ctrl_csr_aliasing 1.720s 836.908us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.870s 4629.701us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.100s 1385.030us 1 1 100.00
adc_ctrl_csr_rw 1.020s 497.988us 1 1 100.00
adc_ctrl_csr_aliasing 1.720s 836.908us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.870s 4629.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 4.940s 8474.152us 1 1 100.00
adc_ctrl_tl_intg_err 2.650s 4559.803us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.650s 4559.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.650s 797.700us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 111137854480991449763701987758080056178599257446195833167413404711630783137144 386
UVM_INFO @ 324501885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 80268080512275179792404861074419858094868680226336757635573369853140589653964 386
UVM_INFO @ 352828880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 111549464455783710537528966631185216266607327481517222591577950856226281694852 386
UVM_INFO @ 497270483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 1790383017544739921443199572913531964292856902119495809022795184465555535368 386
UVM_INFO @ 466718032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 42978563516512413482903230570823733443943362981787816591897650724203100177891 386
UVM_INFO @ 317587360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 65241294892175513675436217816958002968664003750144376779961951203520212473584 386
UVM_INFO @ 440066560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 13644343950781198231705444270598775225163368149625042451172322629824564814064 386
UVM_INFO @ 299618413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 88629883432529577214974484803070449496793190739443920506391629483732272131940 386
UVM_INFO @ 498600704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 51163461482404012055316983331331639088473486691567721854462062099928565035740 406
UVM_INFO @ 797699629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 101220903324919006105006274351860091514604751886368735782145338840393284875483 387
UVM_INFO @ 753719256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---