Simulation Results: aes/masked

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.10 %
  • code
  • 94.19 %
  • assert
  • 98.23 %
  • func
  • 71.89 %
  • block
  • 94.31 %
  • line
  • 95.95 %
  • branch
  • 87.24 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 93.016us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 62.069us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 61.109us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 91.793us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 158.352us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 99.501us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 71.066us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 91.793us 1 1 100.00
aes_csr_aliasing 2.000s 99.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 62.069us 1 1 100.00
aes_config_error 3.000s 162.888us 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 62.069us 1 1 100.00
aes_config_error 3.000s 162.888us 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 209.528us 1 1 100.00
aes_b2b 10.000s 1024.262us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 62.069us 1 1 100.00
aes_config_error 3.000s 162.888us 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
aes_alert_reset 8.000s 1250.781us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 90.828us 1 1 100.00
aes_config_error 3.000s 162.888us 1 1 100.00
aes_alert_reset 8.000s 1250.781us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 159.526us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 271.133us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 8.000s 1250.781us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 209.528us 1 1 100.00
aes_sideload 2.000s 266.028us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 137.435us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 20.000s 3193.976us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 54.150us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 358.300us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 358.300us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 61.109us 1 1 100.00
aes_csr_rw 2.000s 91.793us 1 1 100.00
aes_csr_aliasing 2.000s 99.501us 1 1 100.00
aes_same_csr_outstanding 2.000s 169.514us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 61.109us 1 1 100.00
aes_csr_rw 2.000s 91.793us 1 1 100.00
aes_csr_aliasing 2.000s 99.501us 1 1 100.00
aes_same_csr_outstanding 2.000s 169.514us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 130.044us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 6.000s 818.811us 0 1 0.00
aes_control_fi 2.000s 53.303us 1 1 100.00
aes_cipher_fi 2.000s 68.663us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 223.855us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 223.855us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 223.855us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 223.855us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 150.621us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 742.710us 1 1 100.00
aes_tl_intg_err 2.000s 234.650us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 234.650us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 8.000s 1250.781us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 223.855us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 223.855us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 62.069us 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
aes_alert_reset 8.000s 1250.781us 1 1 100.00
aes_core_fi 2.000s 275.937us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 162.888us 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
aes_core_fi 2.000s 275.937us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 223.855us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 62.891us 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 209.528us 1 1 100.00
aes_sideload 2.000s 266.028us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 62.891us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 62.891us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 62.891us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 62.891us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 62.891us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 209.528us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 6.000s 818.811us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 6.000s 818.811us 0 1 0.00
aes_control_fi 2.000s 53.303us 1 1 100.00
aes_cipher_fi 2.000s 68.663us 1 1 100.00
aes_ctr_fi 2.000s 74.964us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 6.000s 818.811us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 6.000s 818.811us 0 1 0.00
aes_control_fi 2.000s 53.303us 1 1 100.00
aes_cipher_fi 2.000s 68.663us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 68.663us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 6.000s 818.811us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 6.000s 818.811us 0 1 0.00
aes_control_fi 2.000s 53.303us 1 1 100.00
aes_ctr_fi 2.000s 74.964us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 6.000s 818.811us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 6.000s 818.811us 0 1 0.00
aes_control_fi 2.000s 53.303us 1 1 100.00
aes_cipher_fi 2.000s 68.663us 1 1 100.00
aes_ctr_fi 2.000s 74.964us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 8.000s 1250.781us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 6.000s 818.811us 0 1 0.00
aes_control_fi 2.000s 53.303us 1 1 100.00
aes_cipher_fi 2.000s 68.663us 1 1 100.00
aes_ctr_fi 2.000s 74.964us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 6.000s 818.811us 0 1 0.00
aes_control_fi 2.000s 53.303us 1 1 100.00
aes_cipher_fi 2.000s 68.663us 1 1 100.00
aes_ctr_fi 2.000s 74.964us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 6.000s 818.811us 0 1 0.00
aes_control_fi 2.000s 53.303us 1 1 100.00
aes_ctr_fi 2.000s 74.964us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 6.000s 818.811us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 6.000s 818.811us 0 1 0.00
aes_control_fi 2.000s 53.303us 1 1 100.00
aes_cipher_fi 2.000s 68.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 17.000s 3765.207us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 58620099900388151452640259105024351851293230928728237758136786585819354745073 20374
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_stress_all 24422021452848661987929461396985785859193255689858137177831835390818247690630 43402
TEST FAILED MESSAGES DID NOT MATCH
0 80 10 10 0
1 00 3d 3d 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 103206513729325036808326974246724145472907497882934951772067787026806509428273 370
UVM_INFO @ 3765207122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---