Simulation Results: aes/unmasked

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.22 %
  • code
  • 89.54 %
  • assert
  • 97.54 %
  • func
  • 74.57 %
  • block
  • 90.08 %
  • line
  • 92.55 %
  • branch
  • 80.96 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 107.311us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 102.144us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 54.553us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 72.262us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 333.168us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 320.922us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 67.507us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 72.262us 1 1 100.00
aes_csr_aliasing 3.000s 320.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 102.144us 1 1 100.00
aes_config_error 2.000s 110.146us 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 102.144us 1 1 100.00
aes_config_error 2.000s 110.146us 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 74.776us 1 1 100.00
aes_b2b 5.000s 226.528us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 102.144us 1 1 100.00
aes_config_error 2.000s 110.146us 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
aes_alert_reset 2.000s 156.861us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 151.367us 1 1 100.00
aes_config_error 2.000s 110.146us 1 1 100.00
aes_alert_reset 2.000s 156.861us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 91.980us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 1015.284us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 156.861us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 74.776us 1 1 100.00
aes_sideload 2.000s 92.173us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 75.482us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 11.000s 726.547us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 121.167us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 586.826us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 586.826us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 54.553us 1 1 100.00
aes_csr_rw 2.000s 72.262us 1 1 100.00
aes_csr_aliasing 3.000s 320.922us 1 1 100.00
aes_same_csr_outstanding 2.000s 59.736us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 54.553us 1 1 100.00
aes_csr_rw 2.000s 72.262us 1 1 100.00
aes_csr_aliasing 3.000s 320.922us 1 1 100.00
aes_same_csr_outstanding 2.000s 59.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 99.580us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 103.552us 0 1 0.00
aes_control_fi 2.000s 53.777us 1 1 100.00
aes_cipher_fi 2.000s 53.312us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 149.728us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 149.728us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 149.728us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 149.728us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 106.731us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 2768.438us 1 1 100.00
aes_tl_intg_err 3.000s 417.889us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 417.889us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 156.861us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 149.728us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 149.728us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 102.144us 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
aes_alert_reset 2.000s 156.861us 1 1 100.00
aes_core_fi 2.000s 74.595us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 110.146us 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
aes_core_fi 2.000s 74.595us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 149.728us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 139.537us 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 74.776us 1 1 100.00
aes_sideload 2.000s 92.173us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 139.537us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 139.537us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 139.537us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 139.537us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 139.537us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 74.776us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.552us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 103.552us 0 1 0.00
aes_control_fi 2.000s 53.777us 1 1 100.00
aes_cipher_fi 2.000s 53.312us 1 1 100.00
aes_ctr_fi 2.000s 47.691us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.552us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 103.552us 0 1 0.00
aes_control_fi 2.000s 53.777us 1 1 100.00
aes_cipher_fi 2.000s 53.312us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 53.312us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.552us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 103.552us 0 1 0.00
aes_control_fi 2.000s 53.777us 1 1 100.00
aes_ctr_fi 2.000s 47.691us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.552us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 103.552us 0 1 0.00
aes_control_fi 2.000s 53.777us 1 1 100.00
aes_cipher_fi 2.000s 53.312us 1 1 100.00
aes_ctr_fi 2.000s 47.691us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 156.861us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 103.552us 0 1 0.00
aes_control_fi 2.000s 53.777us 1 1 100.00
aes_cipher_fi 2.000s 53.312us 1 1 100.00
aes_ctr_fi 2.000s 47.691us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 103.552us 0 1 0.00
aes_control_fi 2.000s 53.777us 1 1 100.00
aes_cipher_fi 2.000s 53.312us 1 1 100.00
aes_ctr_fi 2.000s 47.691us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 103.552us 0 1 0.00
aes_control_fi 2.000s 53.777us 1 1 100.00
aes_ctr_fi 2.000s 47.691us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 103.552us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 103.552us 0 1 0.00
aes_control_fi 2.000s 53.777us 1 1 100.00
aes_cipher_fi 2.000s 53.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 5.000s 526.904us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 887492440811981411752540523144805501475335307287372364936752537555585084611 3707
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 6808600556118971725343957678115919758650871777896297130184718644364099261663 423
UVM_INFO @ 526903937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---