Simulation Results: alert_handler

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.76 %
  • code
  • 91.02 %
  • assert
  • 98.21 %
  • func
  • 80.04 %
  • line
  • 99.68 %
  • branch
  • 98.40 %
  • cond
  • 91.81 %
  • toggle
  • 89.40 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 6.070s 414.863us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.470s 56.509us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.520s 71.385us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 80.470s 1931.718us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 86.280s 2315.124us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.430s 509.519us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.520s 71.385us 1 1 100.00
alert_handler_csr_aliasing 86.280s 2315.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 14.970s 1217.811us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 47.580s 5261.695us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1740.310s 201696.685us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 15.130s 236.566us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 6.070s 414.863us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 12.880s 225.805us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 39.210s 4814.789us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 89.300s 7378.495us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 832.690s 26747.799us 1 1 100.00
alert_handler_lpg_stub_clk 2106.960s 884866.616us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 302.660s 31305.740us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 5.600s 338.867us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.630s 53.816us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.230s 9.459us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.660s 700.655us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.660s 700.655us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.470s 56.509us 1 1 100.00
alert_handler_csr_rw 3.520s 71.385us 1 1 100.00
alert_handler_csr_aliasing 86.280s 2315.124us 1 1 100.00
alert_handler_same_csr_outstanding 12.170s 1394.252us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.470s 56.509us 1 1 100.00
alert_handler_csr_rw 3.520s 71.385us 1 1 100.00
alert_handler_csr_aliasing 86.280s 2315.124us 1 1 100.00
alert_handler_same_csr_outstanding 12.170s 1394.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 209.020s 19353.882us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 209.020s 19353.882us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 209.020s 19353.882us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 209.020s 19353.882us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 309.560s 15154.358us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
alert_handler_tl_intg_err 26.520s 2387.745us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 26.520s 2387.745us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 209.020s 19353.882us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 6.070s 414.863us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 6.070s 414.863us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 6.070s 414.863us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 6.070s 414.863us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 15.130s 236.566us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 832.690s 26747.799us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 15.130s 236.566us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1740.310s 201696.685us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1740.310s 201696.685us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 7.850s 356.170us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 105.010s 2665.629us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 58535081685127505362651821217270720859861265342802013161042501785228241703403 96
UVM_INFO @ 7378495312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 69455367115382735515177480374679602306334450047100539428451895280838705873852 198
UVM_INFO @ 338867464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 9521779517241441786322096760377339180685096561991681498577506338223640120807 161
UVM_INFO @ 2665628551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---