Simulation Results: chip

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.28 %
  • code
  • 84.28 %
  • assert
  • 97.37 %
  • func
  • 47.18 %
  • line
  • 94.28 %
  • branch
  • 93.70 %
  • cond
  • 89.20 %
  • toggle
  • 87.10 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
75.81%
V2S
100.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 132.290s 2825.831us 1 1 100.00
chip_sw_example_rom 88.480s 3019.888us 1 1 100.00
chip_sw_example_manufacturer 154.150s 3088.303us 1 1 100.00
chip_sw_example_concurrency 143.780s 3045.151us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 297.730s 7466.876us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 198.230s 4369.539us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 565.700s 6442.858us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5206.630s 37152.050us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 55.790s 2420.237us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5206.630s 37152.050us 1 1 100.00
chip_csr_rw 198.230s 4369.539us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.800s 57.785us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 290.990s 4641.327us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 290.990s 4641.327us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 290.990s 4641.327us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 334.700s 3626.820us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 334.700s 3626.820us 1 1 100.00
chip_sw_uart_tx_rx_idx1 345.220s 4776.848us 1 1 100.00
chip_sw_uart_tx_rx_idx2 410.890s 4644.428us 1 1 100.00
chip_sw_uart_tx_rx_idx3 330.840s 4061.396us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 379.990s 4712.620us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 373.030s 4682.438us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 686.990s 9239.517us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 228.840s 4880.987us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 228.840s 4880.987us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 231.580s 3374.623us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 186.650s 3950.397us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 158.080s 3776.417us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 995.160s 15942.566us 1 1 100.00
chip_tap_straps_testunlock0 400.660s 7719.624us 1 1 100.00
chip_tap_straps_rma 159.400s 3761.904us 1 1 100.00
chip_tap_straps_prod 91.280s 3015.121us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 448.070s 6721.442us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 448.070s 6721.442us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 632.710s 8420.583us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1919.010s 15612.864us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 341.870s 4234.913us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 486.940s 5637.446us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3935.770s 18849.703us 1 1 100.00
chip_sw_aes_enc_jitter_en 195.840s 2785.796us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 777.000s 8064.583us 1 1 100.00
chip_sw_hmac_enc_jitter_en 191.040s 2534.583us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1488.670s 13781.874us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 171.310s 2799.349us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 346.040s 5126.952us 1 1 100.00
chip_sw_clkmgr_jitter 174.040s 2852.813us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 161.440s 2573.260us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 436.840s 5210.040us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 273.050s 5752.534us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 143.920s 3171.486us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 273.050s 5752.534us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 171.540s 3506.051us 1 1 100.00
chip_sw_aes_smoketest 202.270s 3692.074us 1 1 100.00
chip_sw_aon_timer_smoketest 161.650s 3392.502us 1 1 100.00
chip_sw_clkmgr_smoketest 164.630s 3067.476us 1 1 100.00
chip_sw_csrng_smoketest 117.990s 2872.842us 1 1 100.00
chip_sw_entropy_src_smoketest 981.860s 6916.828us 1 1 100.00
chip_sw_gpio_smoketest 160.720s 3159.191us 1 1 100.00
chip_sw_hmac_smoketest 199.560s 3583.628us 1 1 100.00
chip_sw_kmac_smoketest 163.090s 2930.868us 1 1 100.00
chip_sw_otbn_smoketest 1207.610s 8451.691us 1 1 100.00
chip_sw_pwrmgr_smoketest 357.190s 6320.431us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 289.680s 6971.899us 1 1 100.00
chip_sw_rv_plic_smoketest 118.690s 2632.433us 1 1 100.00
chip_sw_rv_timer_smoketest 143.790s 2801.522us 1 1 100.00
chip_sw_rstmgr_smoketest 183.880s 2999.986us 1 1 100.00
chip_sw_sram_ctrl_smoketest 124.560s 2980.972us 1 1 100.00
chip_sw_uart_smoketest 215.360s 3234.079us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 127.100s 2753.937us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 316.080s 4505.162us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7512.550s 60061.605us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3145.250s 14538.185us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 28.979s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1074.550s 14981.050us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 950.880s 14761.451us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6651.580s 53210.622us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7577.080s 56438.606us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 61.200s 2360.688us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 61.200s 2360.688us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5206.630s 37152.050us 1 1 100.00
chip_same_csr_outstanding 3003.470s 28520.642us 1 1 100.00
chip_csr_hw_reset 297.730s 7466.876us 1 1 100.00
chip_csr_rw 198.230s 4369.539us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5206.630s 37152.050us 1 1 100.00
chip_same_csr_outstanding 3003.470s 28520.642us 1 1 100.00
chip_csr_hw_reset 297.730s 7466.876us 1 1 100.00
chip_csr_rw 198.230s 4369.539us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 41.660s 1976.493us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.310s 42.336us 1 1 100.00
xbar_smoke_large_delays 55.080s 9902.784us 1 1 100.00
xbar_smoke_slow_rsp 52.670s 5737.403us 1 1 100.00
xbar_random_zero_delays 10.840s 155.837us 1 1 100.00
xbar_random_large_delays 141.140s 26219.423us 1 1 100.00
xbar_random_slow_rsp 211.530s 25660.343us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 27.610s 839.542us 1 1 100.00
xbar_error_and_unmapped_addr 8.210s 105.422us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 23.510s 1167.367us 1 1 100.00
xbar_error_and_unmapped_addr 8.210s 105.422us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 31.660s 1386.034us 1 1 100.00
xbar_access_same_device_slow_rsp 310.330s 39935.960us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 6.180s 39.309us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 320.870s 12311.219us 1 1 100.00
xbar_stress_all_with_error 100.710s 2201.882us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 66.320s 309.283us 1 1 100.00
xbar_stress_all_with_reset_error 199.780s 6535.998us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3145.250s 14538.185us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 403.100s 5997.364us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 443.140s 5491.646us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 46.015s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 9.171s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 7.874s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 8.145s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 9.383s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 63.866s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 40.371s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 10.567s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 9.547s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 11.667s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 67.086s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 60.907s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 38.613s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 45.377s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 39.389s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 21.520s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 26.100s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 19.380s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 23.440s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 20.290s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 18.140s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 22.450s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 20.300s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 19.350s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 21.180s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.030s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.390s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17.950s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 27.580s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 19.960s 10.160us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 74.419s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 75.635s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 65.065s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 64.308s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 74.475s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 5852.510s 28453.526us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3294.160s 16520.884us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5916.140s 28791.840us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3306.080s 16059.971us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3189.680s 34735.166us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3189.680s 34735.166us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 223.390s 3172.344us 1 1 100.00
chip_sw_aes_enc_jitter_en 195.840s 2785.796us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 207.050s 3094.401us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 169.370s 2846.406us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1652.960s 12773.872us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 154.270s 2708.985us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 355.480s 4845.199us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 424.140s 5791.374us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 462.640s 5209.838us 1 1 100.00
chip_plic_all_irqs_10 273.800s 3843.292us 1 1 100.00
chip_plic_all_irqs_20 356.830s 4657.553us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 208.820s 3196.803us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1211.640s 13818.405us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 240.890s 4488.178us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 175.090s 2458.945us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.159s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 935.310s 8072.732us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 838.440s 6954.640us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 794.260s 7388.056us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8200.270s 255756.019us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 291.380s 4830.467us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 357.190s 6320.431us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 291.380s 4830.467us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 376.050s 7291.725us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 376.050s 7291.725us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 295.910s 7564.538us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 452.980s 6392.406us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 628.820s 6395.740us 1 1 100.00
chip_sw_aes_idle 169.370s 2846.406us 1 1 100.00
chip_sw_hmac_enc_idle 197.100s 3378.192us 1 1 100.00
chip_sw_kmac_idle 163.250s 3160.462us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 318.590s 5029.471us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 364.450s 5659.774us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 321.890s 5521.487us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 311.660s 5287.442us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 992.330s 13227.896us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 417.760s 4678.343us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 370.550s 4424.306us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 383.650s 4016.543us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 397.030s 4715.532us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 395.250s 4639.036us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 416.320s 5419.961us 1 1 100.00
chip_sw_ast_clk_outputs 632.710s 8420.583us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 499.910s 10792.814us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 383.650s 4016.543us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 397.030s 4715.532us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 341.870s 4234.913us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 486.940s 5637.446us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3935.770s 18849.703us 1 1 100.00
chip_sw_aes_enc_jitter_en 195.840s 2785.796us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 777.000s 8064.583us 1 1 100.00
chip_sw_hmac_enc_jitter_en 191.040s 2534.583us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1488.670s 13781.874us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 171.310s 2799.349us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 346.040s 5126.952us 1 1 100.00
chip_sw_clkmgr_jitter 174.040s 2852.813us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 117.800s 2699.724us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 385.480s 4827.727us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 552.830s 7014.637us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4247.340s 25208.983us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 182.860s 3738.974us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 152.310s 3022.461us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 598.750s 8423.974us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 210.160s 3623.613us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 340.430s 5374.631us 1 1 100.00
chip_sw_flash_init_reduced_freq 1060.450s 18164.887us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3287.090s 27466.731us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 632.710s 8420.583us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 425.730s 5277.219us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 233.040s 3279.434us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 424.140s 5791.374us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 935.310s 8072.732us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2380.650s 24603.843us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 378.580s 5232.356us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 400.330s 5677.179us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 158.540s 3538.861us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 5441.600s 29842.494us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 163.590s 2655.226us 1 1 100.00
chip_sw_edn_entropy_reqs 677.280s 6056.846us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 163.590s 2655.226us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2380.650s 24603.843us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 125.220s 2833.437us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1107.720s 24980.077us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 507.970s 6022.951us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 486.940s 5637.446us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 368.900s 3613.312us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 341.870s 4234.913us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3833.980s 44376.252us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1107.720s 24980.077us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 213.210s 3091.117us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1545.700s 11517.048us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3077.676us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3833.980s 44376.252us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3077.676us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3077.676us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3077.676us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 157.430s 3077.676us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 424.140s 5791.374us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 174.740s 6203.437us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 525.480s 4827.860us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 402.140s 5481.099us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 402.140s 5481.099us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 187.630s 2819.285us 1 1 100.00
chip_sw_hmac_enc_jitter_en 191.040s 2534.583us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 197.100s 3378.192us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1396.140s 11238.983us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1835.790s 12018.539us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 486.570s 5252.178us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 399.320s 5121.017us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 485.090s 5379.722us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 287.810s 3765.250us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1545.700s 11517.048us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1488.670s 13781.874us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1044.810s 8241.798us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1652.960s 12773.872us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4578.080s 20018.591us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 192.410s 3020.585us 1 1 100.00
chip_sw_kmac_mode_kmac 188.550s 3019.978us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 171.310s 2799.349us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1545.700s 11517.048us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 421.500s 8328.332us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 139.530s 3008.397us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1549.640s 10789.760us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 163.250s 3160.462us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 355.480s 4845.199us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 995.160s 15942.566us 1 1 100.00
chip_tap_straps_rma 159.400s 3761.904us 1 1 100.00
chip_tap_straps_prod 91.280s 3015.121us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 145.370s 2909.329us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 421.500s 8328.332us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 421.500s 8328.332us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 421.500s 8328.332us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1379.230s 10674.257us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 157.430s 3077.676us 0 1 0.00
chip_sw_flash_rma_unlocked 3833.980s 44376.252us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 197.310s 3300.507us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 504.020s 7596.182us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 516.640s 6163.500us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 518.220s 7754.061us 0 1 0.00
chip_sw_lc_ctrl_transition 421.500s 8328.332us 1 1 100.00
chip_sw_keymgr_key_derivation 1545.700s 11517.048us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 319.610s 8285.152us 1 1 100.00
chip_sw_sram_ctrl_execution_main 472.980s 9967.343us 1 1 100.00
chip_prim_tl_access 174.740s 6203.437us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 499.910s 10792.814us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 417.760s 4678.343us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 370.550s 4424.306us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 383.650s 4016.543us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 397.030s 4715.532us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 395.250s 4639.036us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 416.320s 5419.961us 1 1 100.00
chip_tap_straps_dev 995.160s 15942.566us 1 1 100.00
chip_tap_straps_rma 159.400s 3761.904us 1 1 100.00
chip_tap_straps_prod 91.280s 3015.121us 1 1 100.00
chip_rv_dm_lc_disabled 47.520s 1841.937us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 205.750s 3601.446us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 88.230s 3026.306us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 96.020s 2938.950us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 99.910s 3439.004us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1557.370s 35780.060us 1 1 100.00
chip_rv_dm_lc_disabled 47.520s 1841.937us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 622.210s 9067.522us 0 1 0.00
chip_sw_lc_walkthrough_prod 633.310s 8086.462us 0 1 0.00
chip_sw_lc_walkthrough_prodend 629.260s 12597.411us 1 1 100.00
chip_sw_lc_walkthrough_rma 372.110s 6451.258us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1557.370s 35780.060us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 66.180s 2482.413us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 57.820s 1793.366us 1 1 100.00
rom_volatile_raw_unlock 95.946s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3953.950s 17845.015us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3935.770s 18849.703us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 628.820s 6395.740us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 628.820s 6395.740us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 628.820s 6395.740us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 331.930s 4454.240us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 421.500s 8328.332us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1107.720s 24980.077us 1 1 100.00
chip_sw_otbn_mem_scramble 331.930s 4454.240us 1 1 100.00
chip_sw_keymgr_key_derivation 1545.700s 11517.048us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 307.930s 3836.816us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 151.130s 2625.204us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1107.720s 24980.077us 1 1 100.00
chip_sw_otbn_mem_scramble 331.930s 4454.240us 1 1 100.00
chip_sw_keymgr_key_derivation 1545.700s 11517.048us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 307.930s 3836.816us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 151.130s 2625.204us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 421.500s 8328.332us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 303.120s 4613.019us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 145.370s 2909.329us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 197.310s 3300.507us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 504.020s 7596.182us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 516.640s 6163.500us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 518.220s 7754.061us 0 1 0.00
chip_sw_lc_ctrl_transition 421.500s 8328.332us 1 1 100.00
chip_prim_tl_access 174.740s 6203.437us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 174.740s 6203.437us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 923.960s 7711.174us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 152.690s 5342.962us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1242.460s 26868.430us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 276.370s 7347.382us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 355.980s 8261.148us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 486.150s 7994.842us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 838.200s 21711.753us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 381.430s 11026.442us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 376.050s 7291.725us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 804.250s 12544.790us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 395.010s 5251.494us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 152.690s 5342.962us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 278.580s 4371.862us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 503.500s 6736.430us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 334.280s 6904.539us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 187.940s 3162.729us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 206.660s 5347.358us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 753.150s 8643.428us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 879.350s 13161.948us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2231.640s 31321.398us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 153.990s 3227.721us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 424.140s 5791.374us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 319.610s 8285.152us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 319.610s 8285.152us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 879.350s 13161.948us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 206.660s 5347.358us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 395.010s 5251.494us 1 1 100.00
chip_sw_pwrmgr_smoketest 357.190s 6320.431us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 246.020s 4556.753us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 394.790s 5729.470us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 234.860s 4179.606us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1211.640s 13818.405us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 123.040s 2295.330us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 424.140s 5791.374us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 838.440s 6954.640us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 483.700s 4475.058us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 530.260s 5424.330us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 161.670s 3291.333us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 151.130s 2625.204us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 394.790s 5729.470us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 394.790s 5729.470us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 125.350s 2795.626us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 710.720s 10197.021us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 796.710s 14004.009us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 246.020s 4556.753us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 176.160s 3983.671us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1510.490s 12558.075us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 159.400s 3761.904us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 47.520s 1841.937us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 462.640s 5209.838us 1 1 100.00
chip_plic_all_irqs_10 273.800s 3843.292us 1 1 100.00
chip_plic_all_irqs_20 356.830s 4657.553us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 203.430s 3286.081us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 211.020s 3399.388us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3145.250s 14538.185us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 265.000s 4268.464us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 177.630s 3138.837us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 203.550s 3948.324us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 191.440s 2593.907us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 307.930s 3836.816us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 346.040s 5126.952us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 482.170s 8256.910us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 439.890s 8096.346us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 472.980s 9967.343us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 424.140s 5791.374us 1 1 100.00
chip_sw_data_integrity_escalation 448.070s 6721.442us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 753.150s 8643.428us 1 1 100.00
chip_sw_sysrst_ctrl_reset 905.920s 23927.151us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 166.150s 3152.111us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 217.350s 3446.826us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 339.640s 4839.611us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 905.920s 23927.151us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 905.920s 23927.151us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2450.420s 20337.193us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2450.420s 20337.193us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 255.470s 6579.823us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3189.680s 34735.166us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 141.170s 2723.119us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 154.020s 3236.858us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 326.230s 4532.215us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 305.900s 3742.070us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1011.900s 8250.087us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5316.660s 31712.707us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1798.900s 12354.970us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 157.410s 3132.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 160.710s 2537.110us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 131.060s 3100.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9839.690s 68138.531us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1098.400s 6235.499us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 190.490s 4567.816us 0 1 0.00
rom_e2e_jtag_debug_dev 474.460s 7309.060us 0 1 0.00
rom_e2e_jtag_debug_rma 479.130s 7565.190us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 74.660s 2206.378us 0 1 0.00
rom_e2e_jtag_inject_dev 84.950s 2775.758us 0 1 0.00
rom_e2e_jtag_inject_rma 80.080s 2630.624us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 30.161s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 268.020s 3869.988us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 353.360s 2931.853us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 521.720s 3559.530us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 756.960s 5802.909us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 227.280s 2570.213us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 665.480s 5948.884us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 141.140s 2941.086us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 156.180s 2813.847us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 336.050s 6241.485us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 245.280s 5195.062us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 879.350s 13161.948us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 190.490s 4567.816us 0 1 0.00
rom_e2e_jtag_debug_dev 474.460s 7309.060us 0 1 0.00
rom_e2e_jtag_debug_rma 479.130s 7565.190us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 436.570s 5578.521us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 424.140s 5791.374us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5136.910s 38740.637us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5136.910s 38740.637us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 199.560s 3598.088us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 334.700s 3626.820us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3269.390s 19141.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 219.000s 3451.117us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 18.970s 10.220us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 4.840s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 148.270s 3212.672us 1 1 100.00
chip_sw_otp_ctrl_descrambling 156.740s 2465.082us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 208.870s 3608.541us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 10.951s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 166.230s 3218.010us 1 1 100.00
ate_bootstrap_flash_erase 558.430s 10010.180us 0 1 0.00
ate_bootstrap_one_frame 6281.550s 43151.375us 1 1 100.00
ate_bootstrap_disjoint 9140.870s 79126.041us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 58250019152371852484626851320134029508043658989737183679902534612983755626872 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 104494270068099583292466186276603354085386977182630369495514684782488772516734 None
Another command (pid=462080) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=377622) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=466797) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 94335288783039979949297034657840191719148308433569741267168079852322483328397 None
---- STDERR ----
Another command (pid=577609) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 108271050191759573798800496974421847891894554629199836556532075965519251652617 None
---- STDERR ----
Another command (pid=600068) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 40918449846142686994380615230684746264537982792938127862335779573296411939115 None
---- STDERR ----
Another command (pid=600068) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=452229) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 73250690473051174723585112232799046536763634709847088265369862533534491650830 None
Another command (pid=452229) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=570580) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=605033) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 93539512015694660580949196789525208968436640044050766205812148665912170080194 None
Another command (pid=462660) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=387658) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=467427) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 47674159053188543733843842258516570867480958526276937393707060616247630194055 None
Another command (pid=612864) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=622868) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=619889) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 104484046903974304372327351247076131520230175486160857583471385724097478282591 None
---- STDERR ----
Another command (pid=577609) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 51116244396896853773636014253893486829978753860971057715371935918986676988877 None
---- STDERR ----
Another command (pid=577609) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 67211739799538644616932346595426526381162494201720752555736769241186447786995 None
Another command (pid=487890) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=587985) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=472453) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 21020775298832949658905485185712173145007843760722705944744442410677986782900 None
---- STDERR ----
Another command (pid=466797) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 113849673220351755297772938864149757045420117648063322351795064462400293947481 None
---- STDERR ----
Another command (pid=571599) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=422006) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 90809528830506770802550973423176017302521266370885271869053265913539925349354 None
---- STDERR ----
Another command (pid=486549) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 8446136909695286837927757622373991929683525577686458438776535228840843177407 None
Another command (pid=472453) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=568623) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=509786) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 59792017677415026401272759054632376681013339717471725985495609644115105125262 None
Another command (pid=613888) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=624873) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=612864) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 114706804189748413045350665835204072170209280423417074528554872220960488355977 None
Another command (pid=377622) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=466797) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=376734) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 40932147263557627872879677105476029372208721108529423940595568694439004474620 None
Another command (pid=577609) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=582712) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=578796) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 53715657732866088996655134496791463998692038173853852161689620879725969131802 None
Another command (pid=471735) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=431922) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=522197) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 68432179507878887464254187201522288642652414323682414869460622250300099238005 None
---- STDERR ----
Another command (pid=471735) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=522197) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 107197102884783665195116192190932702227940877472017514831257204758170029088383 None
Another command (pid=576520) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=577609) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=578796) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 3655335758649405738043228521108218324995122901782313554935267172306235234698 None
Another command (pid=468834) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=451927) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=471735) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 45710156620529929342091988855247344365381786367329346523967436375133730507328 None
---- STDERR ----
Another command (pid=376329) is running. Waiting for it to complete on the server (server_pid=274317)...
Another command (pid=419769) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 25631023204596842988778393879630454339064846836607737312877142145035621629819 None
---- STDERR ----
Another command (pid=376329) is running. Waiting for it to complete on the server (server_pid=274317)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 7 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 2576552125064920839938643006156614978390964016783961782750646346837282042094 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 22166517253403921792105442219412583946629767650175546297101196187764786362428 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 79685500459117743713562286017353914784693737191680974122157405032863691430009 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 15989450490025260588773490823168098159928884103707721254096957140628054397805 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 4600788950587674610087527475092453882512576404556182030386573287136484426594 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 1300656085506314050944679976389030556050193954631702561907714920572863084178 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 99945317822820640006124779352128311232473740124231101390726075707669930086508 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 17705560972319356276988588709481389401070977035689097540782217035028695036210 368
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 12488856413263172038419500099258364076165360893560199491833917772770105518822 365
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 18388128136953848516085729482402009345226537363264774971304747673501237052449 365
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 52255665204520418532709330687813868345763950938130264165178733501373907796545 326
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 64224300708321763186269043752834171145105170441801991888647435015092150908485 328
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 26487958648719033185587484291847286021298361243454398736591131025205351522480 328
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 4 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 29206499913027113743248355550739323989429847785232220751751485299060638960767 315
UVM_ERROR @ 5347.357500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5347.357500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 88785917169305242818789575435391045616892778664711454747343471819606633506312 327
UVM_ERROR @ 11026.442000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11026.442000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 66419526792078844552020195829175949654801964203682050526671472417427411068642 325
UVM_ERROR @ 8261.148000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8261.148000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 16917058617871458618148289857665784733133158612179147716621253026713781722896 319
UVM_ERROR @ 7291.725000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7291.725000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 15984362265621728823530768686402753496077561046284015910126872677707545400415 369
UVM_INFO @ 9067.522108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 21504154638536407642222382683129825134890093978136305903336923346823505026949 369
UVM_INFO @ 8086.461880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 62455418093238868775177397303816006520025717675877485607652303170504064865021 341
UVM_INFO @ 6451.258188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 87519558959824097363945930357455067351080830985743304780721346635552995985915 326
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 63314765191339659181736395578537000823386013761623943185581546690543418281832 326
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 108880153936092873730001196430952403809490273974752663985883635454986429160605 326
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 85624938268119994649754247231088897238882963678461537390380495444377705947762 313
UVM_ERROR @ 3162.728640 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3162.728640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 78762670149084261228120682862643882333033677551803534856783793597851202382524 329
UVM_ERROR @ 6736.430200 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 6736.430200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 42451337485808905115201056062993857759858378862206872918578612589726923422994 340
UVM_INFO @ 12018.538534 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 74191635318917302669264394632530332215900429956127691110904468630577232596980 334
UVM_INFO @ 20018.591463 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 38554816537371654961130564086050463881720877135912064855816882201079488310875 217
TL item was: req: (cip_tl_seq_item@30710) { a_addr: 'h1051c a_data: 'hdd002280 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h1ae0c d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2360.688328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 89766211206535408285287818203053064369306115692639766190655294984016116932871 224
TL item was: req: (cip_tl_seq_item@30550) { a_addr: 'h10724 a_data: 'h8abe1f02 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc a_opcode: 'h4 a_user: 'h18dc7 d_param: 'h0 d_source: 'hc d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2420.236795 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 17046552709748899925195429764526261005126676709795176271224716064106787004845 363
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 20383081048777023087140945613873029055046402361382717449148930485688007270862 326
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 16702235398458715561739086182630549363543031838160674166603783831846840478996 367
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 75169079058023252808114259090811305786805959618193010045805517407364682201582 326
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 91070882812004838067079252388534502467381691397605810922288022709692870297093 301
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 54223361338140927497608825998368065988884281148492685843304137034470316787669 327
UVM_INFO @ 3138.836895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 18631693941676560618281547482143419410468888521705970274151469766016354215102 309
UVM_INFO @ 3077.676271 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 80389420461130628807460865478526335958910579919593092023872560758920108972330 342
UVM_INFO @ 7754.060700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 18414366750141494279920889840071970198810806604626087249618510670465669664513 316
UVM_ERROR @ 2813.847228 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2813.847228 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 106591098352887943678949923500871378729369075373247012182961417151473200006942 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 59009007162695249536141698591868194780395212807003100520240148186454668301838 318
UVM_ERROR @ 5342.961995 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5342.961995 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 50349744810663666728349042504044068384486151549283714477018582637844490618641 332
UVM_INFO @ 34735.166200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:342)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 72713327454518502543414930251378271475462070184985610162443423975693003998777 307
UVM_INFO @ 2708.985150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 33381648163965767391252217129878003965705399470072299537204539667013609669896 308
UVM_INFO @ 2458.944521 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 75093753066753017803615731423473964207166398920947378950428097203936963212348 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 99824359109337007695721564564675093134667266881412980113926327695263250778486 343
UVM_INFO @ 3869.988203 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 13889721448991517499968288740321782102311421139555326100371096557181148991905 329
UVM_INFO @ 12558.074895 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 28661933029508781414948165751876956488695819417090519754494263803001186801630 215
UVM_INFO @ 1841.936738 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 2756825174057388242978928268227595410844625960771637619984248250412315109529 318
UVM_INFO @ 14981.050410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 26245978929060676125158866000620522587823974209834239523353551318250310221541 329
UVM_INFO @ 14761.451454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 54841370145811354205709732647884373055386295997749329600853065418853249019306 327
UVM_INFO @ 15612.864230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 71870909242199839115639325119583476824733508870433897364459132494850151486580 272
UVM_INFO @ 10010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_exception_c 82244366894595827620767264263657846650830440639415636037433813857762051521501 319
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 5491.645707 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_output 68646309016906306155276489840930470665458805326057226337815319459971896851662 312
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 5997.363770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 21482573477732242407649911946142003903060713754184885483413292786944381952114 325
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 63572871077766305780602367012928627241864337150105939690931231700755562073706 328
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 34678893715858626557640543019292641917461425917499629513976422471097407340147 319
UVM_INFO @ 16520.883894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 66345723065122425244347860366318760174037394569019666568851651795698183118565 327
UVM_ERROR @ 4505.162385 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4505.162385 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---