Simulation Results: clkmgr

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.76 %
  • code
  • 98.29 %
  • assert
  • 95.76 %
  • func
  • 84.22 %
  • line
  • 98.95 %
  • branch
  • 98.48 %
  • cond
  • 94.81 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.830s 24.628us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.860s 59.266us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.760s 20.664us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.370s 326.954us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.150s 30.944us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.020s 111.751us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.760s 20.664us 1 1 100.00
clkmgr_csr_aliasing 1.150s 30.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.870s 21.844us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.900s 30.514us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.710s 37.653us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.680s 47.153us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.830s 24.628us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.820s 2382.717us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.250s 1966.979us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.820s 2382.717us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 53.040s 13367.081us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.710s 32.965us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.250s 196.161us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.250s 196.161us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.860s 59.266us 1 1 100.00
clkmgr_csr_rw 0.760s 20.664us 1 1 100.00
clkmgr_csr_aliasing 1.150s 30.944us 1 1 100.00
clkmgr_same_csr_outstanding 1.110s 108.985us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.860s 59.266us 1 1 100.00
clkmgr_csr_rw 0.760s 20.664us 1 1 100.00
clkmgr_csr_aliasing 1.150s 30.944us 1 1 100.00
clkmgr_same_csr_outstanding 1.110s 108.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.630s 7.682us 0 1 0.00
clkmgr_tl_intg_err 41.110s 10020.369us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 256.473us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 256.473us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 256.473us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 256.473us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 767.640s 200000.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 41.110s 10020.369us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.820s 2382.717us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.250s 1966.979us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.700s 256.473us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.840s 31.333us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.910s 21.612us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.730s 24.702us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.730s 23.959us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.800s 38.726us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.760s 20.664us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.630s 7.682us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.760s 20.664us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.760s 20.664us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.630s 7.682us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.940s 889.295us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 21.220s 2438.148us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 62850210881563468703045572896706043268033889047870630488442320689088970712550 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 26585763515647367292049300921516519246676974703210741356755799897703596817072 79
UVM_INFO @ 7681546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 41911429039957271525381297469991656433680637992158193046261425937709320053836 104
UVM_INFO @ 10020369360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---