Simulation Results: csrng

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.46 %
  • code
  • 92.25 %
  • assert
  • 92.79 %
  • func
  • 74.33 %
  • block
  • 96.89 %
  • line
  • 97.66 %
  • branch
  • 92.26 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 25.236us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 50.678us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 25.660us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 9.000s 242.888us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 139.117us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 16.283us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 25.660us 1 1 100.00
csrng_csr_aliasing 3.000s 139.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
alerts 1 1 100.00
csrng_alert 15.000s 773.065us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 7.000s 444.807us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 7.000s 444.807us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 92.000s 4321.273us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 22.437us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 21.608us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 77.160us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 77.160us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 50.678us 1 1 100.00
csrng_csr_rw 2.000s 25.660us 1 1 100.00
csrng_csr_aliasing 3.000s 139.117us 1 1 100.00
csrng_same_csr_outstanding 3.000s 87.051us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 50.678us 1 1 100.00
csrng_csr_rw 2.000s 25.660us 1 1 100.00
csrng_csr_aliasing 3.000s 139.117us 1 1 100.00
csrng_same_csr_outstanding 3.000s 87.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 89.936us 1 1 100.00
csrng_tl_intg_err 3.000s 243.011us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 53.033us 1 1 100.00
csrng_csr_rw 2.000s 25.660us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 15.000s 773.065us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 92.000s 4321.273us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
csrng_sec_cm 3.000s 89.936us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
csrng_sec_cm 3.000s 89.936us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
csrng_sec_cm 3.000s 89.936us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
csrng_sec_cm 3.000s 89.936us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
csrng_sec_cm 3.000s 89.936us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 15.000s 773.065us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 92.000s 4321.273us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 15.000s 773.065us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 243.011us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
csrng_sec_cm 3.000s 89.936us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
csrng_sec_cm 3.000s 89.936us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 82.830us 1 1 100.00
csrng_err 2.000s 25.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 1.000s 36.412us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 4728492686299450820007383278692103719388084584543782828838361671467986637198 110
UVM_INFO @ 36412407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---