Simulation Results: edn/edn0

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.32 %
  • code
  • 81.90 %
  • assert
  • 96.10 %
  • func
  • 80.95 %
  • line
  • 97.34 %
  • branch
  • 90.93 %
  • cond
  • 85.32 %
  • toggle
  • 86.43 %
  • FSM
  • 49.46 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 27.419us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.900s 18.796us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 14.219us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.730s 326.047us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.380s 35.564us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.050s 25.981us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 14.219us 1 1 100.00
edn_csr_aliasing 1.380s 35.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.090s 130.560us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.090s 130.560us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.090s 130.560us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 65.648us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.100s 161.066us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 127.550us 1 1 100.00
disable 2 2 100.00
edn_disable 0.900s 21.727us 1 1 100.00
edn_disable_auto_req_mode 1.360s 61.539us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.790s 942.041us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 33.384us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.920s 16.305us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.620s 70.916us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.620s 70.916us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.900s 18.796us 1 1 100.00
edn_csr_rw 0.790s 14.219us 1 1 100.00
edn_csr_aliasing 1.380s 35.564us 1 1 100.00
edn_same_csr_outstanding 0.950s 87.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.900s 18.796us 1 1 100.00
edn_csr_rw 0.790s 14.219us 1 1 100.00
edn_csr_aliasing 1.380s 35.564us 1 1 100.00
edn_same_csr_outstanding 0.950s 87.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.200s 1250.021us 1 1 100.00
edn_tl_intg_err 2.230s 98.366us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.090s 17.171us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.100s 161.066us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.200s 1250.021us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.200s 1250.021us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.200s 1250.021us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.200s 1250.021us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.100s 161.066us 1 1 100.00
edn_sec_cm 4.200s 1250.021us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.100s 161.066us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.230s 98.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 28.030s 3678.406us 1 1 100.00