Simulation Results: edn/edn1

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.29 %
  • code
  • 83.14 %
  • assert
  • 98.70 %
  • func
  • 80.04 %
  • line
  • 98.25 %
  • branch
  • 93.72 %
  • cond
  • 90.23 %
  • toggle
  • 86.91 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 27.064us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.930s 55.655us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.780s 58.434us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.880s 322.945us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.140s 19.433us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.080s 35.182us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.780s 58.434us 1 1 100.00
edn_csr_aliasing 1.140s 19.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.020s 230.630us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.020s 230.630us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.020s 230.630us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.700s 34.315us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.930s 23.970us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 147.613us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 44.069us 1 1 100.00
edn_disable_auto_req_mode 0.960s 482.418us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.220s 224.118us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.700s 35.091us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.810s 19.161us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.750s 90.245us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.750s 90.245us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.930s 55.655us 1 1 100.00
edn_csr_rw 0.780s 58.434us 1 1 100.00
edn_csr_aliasing 1.140s 19.433us 1 1 100.00
edn_same_csr_outstanding 1.170s 76.412us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.930s 55.655us 1 1 100.00
edn_csr_rw 0.780s 58.434us 1 1 100.00
edn_csr_aliasing 1.140s 19.433us 1 1 100.00
edn_same_csr_outstanding 1.170s 76.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.460s 190.801us 1 1 100.00
edn_tl_intg_err 1.690s 289.050us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.820s 31.147us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.930s 23.970us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.460s 190.801us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.460s 190.801us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.460s 190.801us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.460s 190.801us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.930s 23.970us 1 1 100.00
edn_sec_cm 2.460s 190.801us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.930s 23.970us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.690s 289.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 45.870s 2991.552us 1 1 100.00