| V1 |
|
83.33% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 2.000s | 167.261us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 114.117us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 2.000s | 44.944us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| entropy_src_csr_bit_bash | 6.000s | 444.982us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| entropy_src_csr_aliasing | 3.000s | 1388.163us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 2.000s | 11.872us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| entropy_src_csr_rw | 2.000s | 44.944us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 1388.163us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 3 | 3 | 100.00 | |||
| entropy_src_smoke | 2.000s | 167.261us | 1 | 1 | 100.00 | |
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 52.000s | 13026.972us | 1 | 1 | 100.00 | |
| firmware_mode | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov | 52.000s | 13026.972us | 1 | 1 | 100.00 | |
| rng_mode | 1 | 1 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| rng_max_rate | 1 | 1 | 100.00 | |||
| entropy_src_rng_max_rate | 89.000s | 14073.165us | 1 | 1 | 100.00 | |
| health_checks | 1 | 1 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| conditioning | 1 | 1 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| interrupts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| entropy_src_intr | 8.000s | 2047.000us | 1 | 1 | 100.00 | |
| alerts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| entropy_src_functional_alerts | 4.000s | 179.417us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| entropy_src_stress_all | 49.000s | 13312.035us | 1 | 1 | 100.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 59.447us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 3.000s | 267.456us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 1.000s | 22.083us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 2.000s | 59.982us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 3.000s | 697.821us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 3.000s | 697.821us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 114.117us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 2.000s | 44.944us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 1388.163us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 328.063us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 2.000s | 114.117us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 2.000s | 44.944us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 3.000s | 1388.163us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 3.000s | 328.063us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_sec_cm | 3.000s | 304.827us | 1 | 1 | 100.00 | |
| entropy_src_tl_intg_err | 2.000s | 67.495us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 2 | 2 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| entropy_src_cfg_regwen | 2.000s | 50.435us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 1 | 1 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| sec_cm_config_redun | 1 | 1 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 52.000s | 13026.972us | 1 | 1 | 100.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 59.447us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 304.827us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 59.447us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 304.827us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 1 | 1 | 100.00 | |||
| entropy_src_rng | 199.000s | 14029.670us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 59.447us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 304.827us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 59.447us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 3.000s | 304.827us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 2.000s | 59.447us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 4.000s | 179.417us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 2.000s | 67.495us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 1 | 1 | 100.00 | |||
| entropy_src_rng_with_xht_rsps | 15.000s | 13522.268us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_stress_all_with_rand_reset | 2.000s | 33.372us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 1 test run | |||
| entropy_src_stress_all_with_rand_reset | 75929548455683869044775090395748862717618565161808983362357330199218744617948 | 120 |
UVM_INFO @ 33371735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts | 1 test run | |||
| entropy_src_csr_mem_rw_with_rand_reset | 87082090029023211491251744473824594248496630387384887727288135834841823968809 | 113 |
UVM_INFO @ 11871840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|