Simulation Results: flash_ctrl

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.51 %
  • code
  • 94.08 %
  • assert
  • 97.02 %
  • func
  • 95.42 %
  • line
  • 95.97 %
  • branch
  • 97.10 %
  • cond
  • 93.40 %
  • toggle
  • 97.54 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 45.860s 42.411us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 17.520s 32.377us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.520s 56.806us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.180s 136.794us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 33.120s 7094.993us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 43.060s 3503.824us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.460s 48.133us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.180s 136.794us 1 1 100.00
flash_ctrl_csr_aliasing 43.060s 3503.824us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 9.240s 18.429us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.360s 21.325us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.980s 147.057us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 21.480s 120.967us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1112.670s 127399.033us 1 1 100.00
flash_ctrl_hw_rma_reset 581.860s 160207.627us 1 1 100.00
flash_ctrl_lcmgr_intg 5.990s 23.598us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1040.530s 284357.562us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 141.060s 3129.080us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.270s 29.846us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2369.830s 225405.039us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 41.790s 113.919us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.310s 65.019us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.570s 33.665us 1 1 100.00
flash_ctrl_re_evict 17.170s 79.055us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 51.170s 90.868us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 51.170s 90.868us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 244.010s 15683.561us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 14.310s 1099.314us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 186.170s 572.411us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 311.490s 21655.060us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 358.720s 1863.064us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1128.550s 2168.985us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.080s 308.035us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 94.780s 7222.605us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.660s 71.124us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.050s 107.393us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 168.150s 492.722us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 125.930s 3559.836us 1 1 100.00
flash_ctrl_otp_reset 63.530s 40.601us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1112.670s 127399.033us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 158.530s 4218.334us 1 1 100.00
flash_ctrl_intr_wr 50.050s 6875.394us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 213.310s 160721.305us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 131.410s 28019.434us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 43.910s 14263.864us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.360s 4044.616us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 13.710s 31.322us 1 1 100.00
flash_ctrl_ro_derr 101.090s 1449.814us 1 1 100.00
flash_ctrl_rw_derr 186.970s 5101.193us 1 1 100.00
flash_ctrl_derr_detect 103.720s 2307.118us 1 1 100.00
flash_ctrl_integrity 363.290s 4167.554us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.360s 189.549us 1 1 100.00
flash_ctrl_ro_serr 95.940s 745.360us 1 1 100.00
flash_ctrl_rw_serr 151.100s 9306.628us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 49.240s 4150.586us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 55.430s 4270.025us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 91.230s 2652.816us 1 1 100.00
flash_ctrl_write_word_sweep 7.610s 69.622us 1 1 100.00
flash_ctrl_read_word_sweep 6.570s 54.754us 1 1 100.00
flash_ctrl_ro 84.990s 3344.722us 1 1 100.00
flash_ctrl_rw 342.010s 4152.654us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.060s 1348.870us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 569.820s 161070.500us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 66.930s 10019.957us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.270s 32.878us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.050s 59.166us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.210s 70.752us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.210s 70.752us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.520s 56.806us 1 1 100.00
flash_ctrl_csr_rw 8.180s 136.794us 1 1 100.00
flash_ctrl_csr_aliasing 43.060s 3503.824us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.980s 180.205us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.520s 56.806us 1 1 100.00
flash_ctrl_csr_rw 8.180s 136.794us 1 1 100.00
flash_ctrl_csr_aliasing 43.060s 3503.824us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.980s 180.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 41.690s 72.859us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 41.690s 72.859us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 41.690s 72.859us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 41.690s 72.859us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 34.880s 311.943us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1736.520s 2952.545us 1 1 100.00
flash_ctrl_tl_intg_err 212.340s 419.865us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 212.340s 419.865us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 212.340s 419.865us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.070s 72.603us 1 1 100.00
flash_ctrl_wr_intg 8.140s 192.511us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 45.860s 42.411us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 63.530s 40.601us 1 1 100.00
flash_ctrl_disable 10.660s 71.124us 1 1 100.00
flash_ctrl_sec_info_access 54.380s 9555.440us 1 1 100.00
flash_ctrl_connect 8.050s 107.393us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.060s 95.456us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.180s 136.794us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 41.690s 72.859us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.180s 136.794us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 41.690s 72.859us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.180s 136.794us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 41.690s 72.859us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.660s 71.124us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.070s 72.603us 1 1 100.00
flash_ctrl_access_after_disable 5.930s 151.928us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 16.120s 69.314us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.660s 71.124us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 14.310s 1099.314us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 342.010s 4152.654us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 151.100s 9306.628us 1 1 100.00
flash_ctrl_rw_derr 186.970s 5101.193us 1 1 100.00
flash_ctrl_integrity 363.290s 4167.554us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1112.670s 127399.033us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1736.520s 2952.545us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1736.520s 2952.545us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1736.520s 2952.545us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1736.520s 2952.545us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.200s 773.754us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 7.620s 21.501us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.120s 73.919us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1736.520s 2952.545us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1736.520s 2952.545us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1736.520s 2952.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 22.170s 1574.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 248.260s 1476.197us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 1 test run
flash_ctrl_phy_host_grant_err 55147156107849085698247569306820233984797902339472084492557761547201977162952 125
UVM_ERROR @ 21501.1 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 21501.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---