Simulation Results: hmac

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.91 %
  • code
  • 97.73 %
  • assert
  • 97.60 %
  • func
  • 44.39 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.620s 10112.779us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.810s 34.146us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.730s 29.171us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.330s 908.653us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.550s 570.747us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 186.610s 96947.335us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.730s 29.171us 1 1 100.00
hmac_csr_aliasing 6.550s 570.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 63.520s 61468.491us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 3.170s 92.094us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.890s 247.705us 1 1 100.00
hmac_test_sha384_vectors 21.340s 311.376us 1 1 100.00
hmac_test_sha512_vectors 331.930s 13539.318us 1 1 100.00
hmac_test_hmac256_vectors 10.250s 1387.815us 1 1 100.00
hmac_test_hmac384_vectors 6.700s 1194.140us 1 1 100.00
hmac_test_hmac512_vectors 9.830s 1904.442us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 9.670s 3561.474us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 746.980s 35385.558us 1 1 100.00
error 1 1 100.00
hmac_error 79.560s 10123.962us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 38.570s 1539.829us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.620s 10112.779us 1 1 100.00
hmac_long_msg 63.520s 61468.491us 1 1 100.00
hmac_back_pressure 3.170s 92.094us 1 1 100.00
hmac_datapath_stress 746.980s 35385.558us 1 1 100.00
hmac_burst_wr 9.670s 3561.474us 1 1 100.00
hmac_stress_all 746.700s 8597.210us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.620s 10112.779us 1 1 100.00
hmac_long_msg 63.520s 61468.491us 1 1 100.00
hmac_back_pressure 3.170s 92.094us 1 1 100.00
hmac_datapath_stress 746.980s 35385.558us 1 1 100.00
hmac_wipe_secret 38.570s 1539.829us 1 1 100.00
hmac_test_sha256_vectors 9.890s 247.705us 1 1 100.00
hmac_test_sha384_vectors 21.340s 311.376us 1 1 100.00
hmac_test_sha512_vectors 331.930s 13539.318us 1 1 100.00
hmac_test_hmac256_vectors 10.250s 1387.815us 1 1 100.00
hmac_test_hmac384_vectors 6.700s 1194.140us 1 1 100.00
hmac_test_hmac512_vectors 9.830s 1904.442us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.620s 10112.779us 1 1 100.00
hmac_long_msg 63.520s 61468.491us 1 1 100.00
hmac_back_pressure 3.170s 92.094us 1 1 100.00
hmac_datapath_stress 746.980s 35385.558us 1 1 100.00
hmac_burst_wr 9.670s 3561.474us 1 1 100.00
hmac_error 79.560s 10123.962us 1 1 100.00
hmac_wipe_secret 38.570s 1539.829us 1 1 100.00
hmac_test_sha256_vectors 9.890s 247.705us 1 1 100.00
hmac_test_sha384_vectors 21.340s 311.376us 1 1 100.00
hmac_test_sha512_vectors 331.930s 13539.318us 1 1 100.00
hmac_test_hmac256_vectors 10.250s 1387.815us 1 1 100.00
hmac_test_hmac384_vectors 6.700s 1194.140us 1 1 100.00
hmac_test_hmac512_vectors 9.830s 1904.442us 1 1 100.00
hmac_stress_all 746.700s 8597.210us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 746.700s 8597.210us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.620s 15.960us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.660s 26.051us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.550s 288.824us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.550s 288.824us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.810s 34.146us 1 1 100.00
hmac_csr_rw 0.730s 29.171us 1 1 100.00
hmac_csr_aliasing 6.550s 570.747us 1 1 100.00
hmac_same_csr_outstanding 1.500s 67.283us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.810s 34.146us 1 1 100.00
hmac_csr_rw 0.730s 29.171us 1 1 100.00
hmac_csr_aliasing 6.550s 570.747us 1 1 100.00
hmac_same_csr_outstanding 1.500s 67.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 139.774us 1 1 100.00
hmac_tl_intg_err 2.980s 547.291us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.980s 547.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.620s 10112.779us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.460s 514.478us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 233.330s 21618.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.050s 940.986us 1 1 100.00