Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.55 %
  • code
  • 83.80 %
  • assert
  • 94.97 %
  • func
  • 92.88 %
  • line
  • 97.20 %
  • branch
  • 93.56 %
  • cond
  • 79.15 %
  • toggle
  • 85.53 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.400s 245.554us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.190s 17.216us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.730s 45.188us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.490s 25.698us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 41.653us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.150s 19.811us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.730s 45.188us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 41.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.710s 915.156us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.760s 237.889us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.870s 22.355us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.850s 640.983us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.830s 204.172us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_ctrl_prog_failure 2.850s 640.983us 1 1 100.00
lc_ctrl_errors 3.830s 204.172us 1 1 100.00
lc_ctrl_security_escalation 7.770s 2822.562us 1 1 100.00
lc_ctrl_jtag_state_failure 19.210s 12474.818us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.270s 510.267us 1 1 100.00
lc_ctrl_jtag_errors 15.220s 11364.125us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.110s 1013.721us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.500s 1227.061us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.270s 510.267us 1 1 100.00
lc_ctrl_jtag_errors 15.220s 11364.125us 1 1 100.00
lc_ctrl_jtag_access 3.680s 705.252us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 27.620s 2996.127us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.450s 52.156us 1 1 100.00
lc_ctrl_jtag_csr_rw 4.110s 347.299us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.760s 1669.781us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.470s 2254.728us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.300s 56.193us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.380s 70.675us 1 1 100.00
lc_ctrl_jtag_alert_test 0.790s 107.690us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.330s 120.741us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.860s 46.572us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 45.550s 2339.675us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.910s 20.523us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.940s 578.559us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.940s 578.559us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.190s 17.216us 1 1 100.00
lc_ctrl_csr_rw 0.730s 45.188us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 41.653us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.330s 33.456us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.190s 17.216us 1 1 100.00
lc_ctrl_csr_rw 0.730s 45.188us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 41.653us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.330s 33.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.330s 299.453us 1 1 100.00
lc_ctrl_tl_intg_err 2.460s 421.687us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.460s 421.687us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.760s 237.889us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_ctrl_sec_cm 6.330s 299.453us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_ctrl_sec_cm 6.330s 299.453us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_ctrl_sec_cm 6.330s 299.453us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_ctrl_sec_cm 6.330s 299.453us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_ctrl_sec_cm 6.330s 299.453us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_ctrl_sec_cm 6.330s 299.453us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_ctrl_sec_cm 6.330s 299.453us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.510s 184.131us 1 1 100.00
lc_ctrl_sec_cm 6.330s 299.453us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.770s 2822.562us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.710s 915.156us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.500s 1227.061us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.300s 783.135us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.300s 783.135us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.150s 2541.698us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.110s 1035.361us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.110s 1035.361us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 13.650s 1944.462us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 89167930637537097525139088686628201278172286259270077946040047574907897567361 3877
UVM_INFO @ 1944461733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---