Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.57 %
  • code
  • 83.50 %
  • assert
  • 94.97 %
  • func
  • 93.24 %
  • line
  • 97.17 %
  • branch
  • 93.66 %
  • cond
  • 78.78 %
  • toggle
  • 84.35 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.570s 125.192us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.790s 41.957us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.800s 45.747us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.840s 109.867us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 20.326us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.100s 68.165us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.800s 45.747us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 20.326us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.020s 63.521us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.440s 325.004us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.880s 14.211us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.920s 171.877us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.920s 3051.382us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_ctrl_prog_failure 1.920s 171.877us 1 1 100.00
lc_ctrl_errors 7.920s 3051.382us 1 1 100.00
lc_ctrl_security_escalation 4.770s 372.950us 1 1 100.00
lc_ctrl_jtag_state_failure 20.170s 23966.013us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 114.723us 1 1 100.00
lc_ctrl_jtag_errors 36.540s 7812.859us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.330s 1062.152us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.620s 468.381us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.000s 114.723us 1 1 100.00
lc_ctrl_jtag_errors 36.540s 7812.859us 1 1 100.00
lc_ctrl_jtag_access 3.960s 170.953us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 20.710s 3560.663us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.250s 425.417us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.240s 142.554us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.910s 679.892us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.400s 284.672us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.220s 50.983us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.550s 1227.248us 1 1 100.00
lc_ctrl_jtag_alert_test 1.800s 332.342us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.720s 3308.293us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.970s 15.579us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 65.360s 11450.300us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.990s 88.790us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.390s 50.549us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.390s 50.549us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 41.957us 1 1 100.00
lc_ctrl_csr_rw 0.800s 45.747us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 20.326us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.280s 108.557us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 41.957us 1 1 100.00
lc_ctrl_csr_rw 0.800s 45.747us 1 1 100.00
lc_ctrl_csr_aliasing 1.120s 20.326us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.280s 108.557us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.240s 221.260us 1 1 100.00
lc_ctrl_tl_intg_err 2.870s 630.211us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.870s 630.211us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.440s 325.004us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_ctrl_sec_cm 6.240s 221.260us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_ctrl_sec_cm 6.240s 221.260us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_ctrl_sec_cm 6.240s 221.260us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_ctrl_sec_cm 6.240s 221.260us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_ctrl_sec_cm 6.240s 221.260us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_ctrl_sec_cm 6.240s 221.260us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_ctrl_sec_cm 6.240s 221.260us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.470s 302.528us 1 1 100.00
lc_ctrl_sec_cm 6.240s 221.260us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.770s 372.950us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.020s 63.521us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.620s 468.381us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.790s 1785.014us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.790s 1785.014us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.710s 426.275us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.030s 3145.584us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.030s 3145.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 15.040s 2332.144us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 60767662022507653941556569817753199830989258265877514195843018527665127428619 2842
UVM_INFO @ 2332143951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---