Simulation Results: otbn

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.79 %
  • code
  • 81.88 %
  • assert
  • 90.04 %
  • func
  • 97.46 %
  • block
  • 97.76 %
  • line
  • 97.95 %
  • branch
  • 82.08 %
  • toggle
  • 81.29 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 76.456us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 22.973us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 34.000s 47.069us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 34.000s 38.665us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 35.000s 139.312us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 35.000s 18.239us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 37.000s 398.319us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 34.000s 38.665us 1 1 100.00
otbn_csr_aliasing 35.000s 18.239us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 50.000s 2194.489us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 28.000s 1336.300us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 22.000s 107.383us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 53.000s 773.619us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 27.000s 72.773us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 89.000s 327.232us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 34.000s 83.202us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.138us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 67.055us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 35.000s 16.571us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 26.000s 17.427us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 115.178us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 115.178us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 34.000s 47.069us 1 1 100.00
otbn_csr_rw 34.000s 38.665us 1 1 100.00
otbn_csr_aliasing 35.000s 18.239us 1 1 100.00
otbn_same_csr_outstanding 4.000s 17.693us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 34.000s 47.069us 1 1 100.00
otbn_csr_rw 34.000s 38.665us 1 1 100.00
otbn_csr_aliasing 35.000s 18.239us 1 1 100.00
otbn_same_csr_outstanding 4.000s 17.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 30.000s 20.364us 1 1 100.00
otbn_dmem_err 40.000s 80.624us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 40.000s 74.455us 1 1 100.00
otbn_controller_ispr_rdata_err 44.000s 116.847us 1 1 100.00
otbn_mac_bignum_acc_err 28.000s 34.847us 1 1 100.00
otbn_urnd_err 9.000s 20.010us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 35.000s 18.590us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 14.000s 39.035us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 45.955us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
otbn_tl_intg_err 18.000s 708.088us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 24.000s 249.270us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 76.456us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 40.000s 80.624us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 30.000s 20.364us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 18.000s 708.088us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 34.000s 83.202us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 30.000s 20.364us 1 1 100.00
otbn_dmem_err 40.000s 80.624us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.138us 1 1 100.00
otbn_illegal_mem_acc 35.000s 18.590us 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 22.973us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 30.000s 20.364us 1 1 100.00
otbn_dmem_err 40.000s 80.624us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.138us 1 1 100.00
otbn_illegal_mem_acc 35.000s 18.590us 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 34.000s 83.202us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 30.000s 20.364us 1 1 100.00
otbn_dmem_err 40.000s 80.624us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 17.138us 1 1 100.00
otbn_illegal_mem_acc 35.000s 18.590us 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 22.973us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 35.000s 40.344us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 14.000s 52.602us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 37.000s 129.426us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 37.000s 129.426us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 12.000s 34.196us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 55.319us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 16.000s 129.758us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 16.000s 129.758us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 25.283us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 22.973us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 22.973us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 22.973us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 27.000s 72.773us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 22.973us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 22.973us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 19.000s 102.784us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 22.973us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 341.000s 3490.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 43.000s 288.136us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 40.175us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 95234203211387798157973910376970424191442830968959631574176898473517073749009 190
UVM_INFO @ 288135848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---