Simulation Results: otp_ctrl

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.26 %
  • code
  • 78.90 %
  • assert
  • 94.69 %
  • func
  • 73.20 %
  • line
  • 88.65 %
  • branch
  • 83.45 %
  • cond
  • 90.16 %
  • toggle
  • 85.19 %
  • FSM
  • 47.05 %
Validation stages
V1
88.89%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.300s 115.160us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.630s 469.064us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.290s 268.582us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.830s 88.917us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.040s 1103.376us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.940s 115.681us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.100s 237.249us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.830s 88.917us 1 1 100.00
otp_ctrl_csr_aliasing 2.940s 115.681us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.160s 71.656us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.600s 559.962us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.630s 1023.086us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.130s 153.172us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 8.690s 3963.702us 1 1 100.00
otp_ctrl_check_fail 13.800s 11430.175us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.500s 4681.526us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 5.720s 381.275us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 4.310s 629.780us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 10.680s 2106.136us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 31.280s 2768.529us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 6.200s 4874.448us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 3.950s 258.767us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 98.030s 21018.271us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.340s 59.799us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.560s 82.732us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.250s 111.648us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.250s 111.648us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.290s 268.582us 1 1 100.00
otp_ctrl_csr_rw 1.830s 88.917us 1 1 100.00
otp_ctrl_csr_aliasing 2.940s 115.681us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.010s 147.665us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.290s 268.582us 1 1 100.00
otp_ctrl_csr_rw 1.830s 88.917us 1 1 100.00
otp_ctrl_csr_aliasing 2.940s 115.681us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.010s 147.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
otp_ctrl_tl_intg_err 6.500s 651.804us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 6.500s 651.804us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.630s 469.064us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.630s 469.064us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
otp_ctrl_macro_errs 6.200s 4874.448us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
otp_ctrl_macro_errs 6.200s 4874.448us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.460s 310.490us 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.130s 153.172us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 13.800s 11430.175us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 5.720s 381.275us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 5.720s 381.275us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 5.720s 381.275us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 5.720s 381.275us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 5.720s 381.275us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.630s 469.064us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 5.720s 381.275us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.630s 469.064us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.820s 13536.281us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.500s 4681.526us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.630s 469.064us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.630s 469.064us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 6.200s 4874.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.440s 8061.444us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.260s 26.888us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 71975646410943586735354063504869655723349926469371653007879754201158826526616 92
UVM_INFO @ 26887797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 16097333690866095320095689740186286901830833075902049208013443254106882824708 98
UVM_INFO @ 237248557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---