Simulation Results: pwrmgr

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.36 %
  • code
  • 97.48 %
  • assert
  • 97.39 %
  • func
  • 97.20 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.32 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.660s 59.310us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.710s 38.204us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.680s 22.175us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.660s 666.523us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.920s 84.619us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.860s 54.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.680s 22.175us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 84.619us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.710s 273.219us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.710s 273.219us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.860s 41.536us 1 1 100.00
pwrmgr_lowpower_invalid 0.810s 42.560us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.700s 70.168us 1 1 100.00
pwrmgr_reset_invalid 0.700s 124.873us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.700s 70.168us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.240s 316.340us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.760s 233.966us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.680s 75.630us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 2.820s 3250.660us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 42.701us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.490s 41.859us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.490s 41.859us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 38.204us 1 1 100.00
pwrmgr_csr_rw 0.680s 22.175us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 84.619us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 75.151us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 38.204us 1 1 100.00
pwrmgr_csr_rw 0.680s 22.175us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 84.619us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 75.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.210s 567.006us 1 1 100.00
pwrmgr_sec_cm 1.470s 707.441us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.470s 707.441us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.470s 707.441us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.210s 567.006us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.840s 1043.710us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 1.240s 316.340us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.530s 2760.161us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.850s 76.075us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.700s 29.534us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.470s 707.441us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.470s 707.441us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.470s 707.441us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.630s 55.298us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.610s 62.424us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.900s 346.061us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.680s 22.175us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.680s 22.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.730s 102.595us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 9.000s 9534.146us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 10107977436258057555528281120973125483135823968534024819184460102754792486400 79
UVM_ERROR @ 102595056 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 102595056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---