Simulation Results: rstmgr

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.62 %
  • code
  • 99.33 %
  • assert
  • 98.53 %
  • func
  • 98.01 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.730s 297.070us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.140s 150.319us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.020s 92.412us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.940s 2847.970us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.460s 229.577us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.060s 112.188us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.020s 92.412us 1 1 100.00
rstmgr_csr_aliasing 1.460s 229.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.810s 176.149us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.410s 174.865us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.400s 336.066us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.870s 1105.626us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.870s 1105.626us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.870s 1105.626us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.870s 1105.626us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 19.900s 9319.058us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.680s 75.650us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.080s 425.995us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.080s 425.995us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.140s 150.319us 1 1 100.00
rstmgr_csr_rw 1.020s 92.412us 1 1 100.00
rstmgr_csr_aliasing 1.460s 229.577us 1 1 100.00
rstmgr_same_csr_outstanding 0.920s 139.572us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.140s 150.319us 1 1 100.00
rstmgr_csr_rw 1.020s 92.412us 1 1 100.00
rstmgr_csr_aliasing 1.460s 229.577us 1 1 100.00
rstmgr_same_csr_outstanding 0.920s 139.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.630s 9150.810us 1 1 100.00
rstmgr_tl_intg_err 1.640s 513.823us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.630s 9150.810us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.630s 9150.810us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.640s 513.823us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.090s 120.410us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.800s 2529.462us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.110s 301.834us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.630s 9150.810us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.020s 92.412us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.020s 92.412us 1 1 100.00