Simulation Results: rv_timer

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.38 %
  • code
  • 94.66 %
  • assert
  • 98.41 %
  • func
  • 87.06 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.680s 40.898us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.610s 79.032us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.710s 20.420us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.850s 356.686us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.670s 19.466us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.720s 43.587us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.710s 20.420us 1 1 100.00
rv_timer_csr_aliasing 0.670s 19.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.580s 66.959us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.810s 498.411us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 1.370s 1020.330us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 1.370s 1020.330us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.840s 1805.059us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.550s 18.291us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.600s 47.402us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.010s 177.158us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.010s 177.158us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 79.032us 1 1 100.00
rv_timer_csr_rw 0.710s 20.420us 1 1 100.00
rv_timer_csr_aliasing 0.670s 19.466us 1 1 100.00
rv_timer_same_csr_outstanding 0.600s 69.473us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 79.032us 1 1 100.00
rv_timer_csr_rw 0.710s 20.420us 1 1 100.00
rv_timer_csr_aliasing 0.670s 19.466us 1 1 100.00
rv_timer_same_csr_outstanding 0.600s 69.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.880s 44.484us 1 1 100.00
rv_timer_tl_intg_err 0.770s 52.364us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.770s 52.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.570s 223.484us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.600s 86.114us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 14.800s 1805.336us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 113649387543477085126713936306750920881291865188659059031850488630886639694885 75
UVM_INFO @ 223484118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 67805258416739861942145463788753340186846407655006801563817519935168294378774 75
UVM_INFO @ 66959017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 83026379650926246964394481309776179486701945621481266278985016639301246155349 75
UVM_INFO @ 86114418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---