Simulation Results: spi_device/1r1w

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.10 %
  • code
  • 90.59 %
  • assert
  • 95.40 %
  • func
  • 69.30 %
  • line
  • 98.82 %
  • branch
  • 98.11 %
  • cond
  • 95.45 %
  • toggle
  • 71.19 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 35.990s 3222.175us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.800s 15.118us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.600s 90.079us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 29.620s 15309.208us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.380s 210.881us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.350s 51.647us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.600s 90.079us 1 1 100.00
spi_device_csr_aliasing 4.380s 210.881us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.670s 11.294us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.440s 92.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.660s 21.898us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.810s 5.527us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.790s 6.956us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.120s 405.551us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.120s 405.551us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.530s 431.715us 1 1 100.00
spi_device_tpm_sts_read 0.930s 42.600us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 7.040s 1808.308us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.880s 1246.114us 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.550s 642.410us 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.550s 642.410us 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.600s 226.361us 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.600s 226.361us 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.600s 226.361us 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.600s 226.361us 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.600s 226.361us 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.010s 2116.891us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 8.540s 1629.632us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 8.540s 1629.632us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 8.540s 1629.632us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.780s 1395.177us 1 1 100.00
spi_device_read_buffer_direct 3.970s 3872.843us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 8.540s 1629.632us 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 16.770s 2510.969us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.960s 2627.822us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.960s 2627.822us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 29.200s 2231.822us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 35.990s 3222.175us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 35.890s 2938.817us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 252.450s 38378.557us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.640s 11.449us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.880s 15.311us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.440s 90.518us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.440s 90.518us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 15.118us 1 1 100.00
spi_device_csr_rw 1.600s 90.079us 1 1 100.00
spi_device_csr_aliasing 4.380s 210.881us 1 1 100.00
spi_device_same_csr_outstanding 2.620s 140.968us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.800s 15.118us 1 1 100.00
spi_device_csr_rw 1.600s 90.079us 1 1 100.00
spi_device_csr_aliasing 4.380s 210.881us 1 1 100.00
spi_device_same_csr_outstanding 2.620s 140.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.630s 3223.738us 1 1 100.00
spi_device_tl_intg_err 6.760s 706.252us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.760s 706.252us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 67922801210764586508534183358181064655089237556902155229114376095065285346191 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 4446818 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 4446818 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[967])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 28411484673554306357278542775293801808833767093437196275003857791917573437487 76
UVM_ERROR @ 4289818 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf34bab [111100110100101110101011] vs 0x0 [0])
UVM_ERROR @ 4330818 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3c73f3 [1111000111001111110011] vs 0x0 [0])
UVM_ERROR @ 4416818 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa3a460 [101000111010010001100000] vs 0x0 [0])
UVM_ERROR @ 4439818 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe8c379 [111010001100001101111001] vs 0x0 [0])