Simulation Results: sram_ctrl/ret

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.54 %
  • code
  • 82.35 %
  • assert
  • 97.26 %
  • func
  • 95.00 %
  • block
  • 93.76 %
  • line
  • 94.91 %
  • branch
  • 89.51 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 271.163us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 15.028us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.810us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 101.457us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 37.364us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 98.907us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.810us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 37.364us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 394.643us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 270.313us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 321.230us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 121.000s 2638.345us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 1869.954us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 485.135us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 986.109us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 1223.523us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 27.647us 1 1 100.00
sram_ctrl_partial_access_b2b 282.000s 22220.737us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 69.141us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 27.689us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 23.867us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 2219.606us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 100.171us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 33.000s 3807.162us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 15.023us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 26.408us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 26.408us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.028us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.810us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 37.364us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 81.949us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.028us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.810us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 37.364us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 81.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 3177.310us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 381.725us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 947.863us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 381.725us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 947.863us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 2219.606us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 2219.606us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.810us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1223.523us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1223.523us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 1223.523us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 986.109us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 33.904us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 3177.310us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 266.548us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 271.163us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 271.163us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 1223.523us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 381.725us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 986.109us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 381.725us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 381.725us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 271.163us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 381.725us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 39.000s 4859.815us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 91364881353581646652206978785286153036249280213064769107059847266701196044186 86
UVM_INFO @ 69140993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 20000354053259033118709513392055799672930963563199122737630778444714389228563 86
UVM_INFO @ 27688925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 23079138470848865356171922848344769815117612748560421827420556230105015529711 86
UVM_INFO @ 23866821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---