Simulation Results: sysrst_ctrl

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.42 %
  • code
  • 93.26 %
  • assert
  • 94.64 %
  • func
  • 74.36 %
  • line
  • 97.71 %
  • branch
  • 97.59 %
  • cond
  • 95.36 %
  • toggle
  • 100.00 %
  • FSM
  • 75.64 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.910s 2113.727us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.510s 2450.908us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.130s 2390.558us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.180s 2565.101us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.800s 6216.109us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.210s 2053.510us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 194.310s 76192.576us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.700s 2703.923us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.510s 2079.153us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.210s 2053.510us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.700s 2703.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 28.590s 36729.654us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 152.370s 177872.841us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.370s 3513.620us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.960s 3483.308us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.100s 2511.781us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.370s 2114.341us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.290s 5771.264us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.270s 2624.273us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.680s 5819.001us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 63.340s 38886.170us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 159.040s 101789.367us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.500s 2033.887us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.720s 2038.888us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.030s 2162.092us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.030s 2162.092us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.800s 6216.109us 1 1 100.00
sysrst_ctrl_csr_rw 4.210s 2053.510us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.700s 2703.923us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.110s 4698.423us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.800s 6216.109us 1 1 100.00
sysrst_ctrl_csr_rw 4.210s 2053.510us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.700s 2703.923us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.110s 4698.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 9.730s 22081.800us 1 1 100.00
sysrst_ctrl_tl_intg_err 36.230s 42442.318us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 36.230s 42442.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.710s 6976.080us 1 1 100.00