Simulation Results: uart

 
06/07/2026 15:30:30 DVSim: v1.49.12 sha: fa5c0ef json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.02 %
  • code
  • 90.04 %
  • assert
  • 97.12 %
  • func
  • 40.90 %
  • line
  • 98.86 %
  • branch
  • 95.80 %
  • cond
  • 91.02 %
  • toggle
  • 74.49 %
Validation stages
V1
100.00%
V2
86.36%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 16.650s 11069.330us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.680s 45.386us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.590s 15.952us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.130s 541.132us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.830s 15.495us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.640s 116.601us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.590s 15.952us 1 1 100.00
uart_csr_aliasing 0.830s 15.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 2.460s 20401.417us 1 1 100.00
parity 2 2 100.00
uart_smoke 16.650s 11069.330us 1 1 100.00
uart_tx_rx 2.460s 20401.417us 1 1 100.00
parity_error 1 2 50.00
uart_intr 15.120s 14635.613us 1 1 100.00
uart_rx_parity_err 32.440s 600000.000us 0 1 0.00
watermark 2 2 100.00
uart_tx_rx 2.460s 20401.417us 1 1 100.00
uart_intr 15.120s 14635.613us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 59.810s 55529.325us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 18.340s 137991.675us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 15.350s 67571.949us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 15.120s 14635.613us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 15.120s 14635.613us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 15.120s 14635.613us 1 1 100.00
perf 1 1 100.00
uart_perf 53.650s 3820.741us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.110s 241.439us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.110s 241.439us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.470s 2864.449us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.370s 1790.873us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.820s 2674.833us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.090s 2841.692us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 261.830s 203445.897us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 750.990s 236582.005us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.650s 26.898us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.700s 15.027us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.340s 224.662us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.340s 224.662us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.680s 45.386us 1 1 100.00
uart_csr_rw 0.590s 15.952us 1 1 100.00
uart_csr_aliasing 0.830s 15.495us 1 1 100.00
uart_same_csr_outstanding 1.010s 102.878us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.680s 45.386us 1 1 100.00
uart_csr_rw 0.590s 15.952us 1 1 100.00
uart_csr_aliasing 0.830s 15.495us 1 1 100.00
uart_same_csr_outstanding 1.010s 102.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.800s 186.248us 1 1 100.00
uart_tl_intg_err 1.100s 149.945us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.100s 149.945us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 8.050s 1602.419us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 2 test runs
uart_noise_filter 14314873402734821799474530355728684942583056436579542099479774076456355236026 74
UVM_ERROR @ 68218660 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 209968660 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (243 [0xf3] vs 155 [0x9b]) reg name: uart_reg_block.rdata
UVM_ERROR @ 257328660 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 257348660 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_stress_all 3002902948035241661605457411136705040593302841405557512283402479968272870081 98
UVM_ERROR @ 236554027279 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 236554848307 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 236555690387 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 236556532467 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
uart_rx_parity_err 80908257244326745034844768287467106835240730065032911012021440893441035245129 83
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---