Simulation Results: adc_ctrl

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.89 %
  • code
  • 93.33 %
  • assert
  • 91.09 %
  • func
  • 13.24 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 86.06 %
  • toggle
  • 99.76 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.630s 5865.250us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.020s 1202.411us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.000s 403.235us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 31.580s 53190.242us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.710s 850.243us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.020s 654.654us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.000s 403.235us 1 1 100.00
adc_ctrl_csr_aliasing 1.710s 850.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.210s 410.712us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.060s 357.620us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.090s 342.192us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.820s 442.520us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.660s 318.653us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.810s 469.026us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.220s 458.984us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.810s 482.825us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 4.030s 4763.744us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 4.440s 31881.858us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 47.910s 126486.917us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 0.770s 774.028us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.650s 353.646us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.740s 453.722us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.600s 427.615us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.600s 427.615us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.020s 1202.411us 1 1 100.00
adc_ctrl_csr_rw 1.000s 403.235us 1 1 100.00
adc_ctrl_csr_aliasing 1.710s 850.243us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.410s 4885.656us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.020s 1202.411us 1 1 100.00
adc_ctrl_csr_rw 1.000s 403.235us 1 1 100.00
adc_ctrl_csr_aliasing 1.710s 850.243us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.410s 4885.656us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 9.770s 7148.006us 1 1 100.00
adc_ctrl_tl_intg_err 13.720s 8294.847us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 13.720s 8294.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 6.270s 3228.226us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 33621114479726846445446978460763379456730562447004063462943126023450359380130 386
UVM_INFO @ 410711516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 66582774255613318167453547039419268353622569334763107664797549820035318231548 386
UVM_INFO @ 357620334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 20639310091435744743962979606778814738386103084804695176180227640602521292082 386
UVM_INFO @ 342192391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 83020728698166331607989311358062416660092495497895269122869829920957474756415 386
UVM_INFO @ 442520296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 8703537056080238245429215388048084050993513048263592927868575266926951986567 386
UVM_INFO @ 318653284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 53565915582029151538611486214907538962591895492728428737954174472869238030483 386
UVM_INFO @ 469026231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 109424133472302502324290217624200055823302252722934083469922367586028560289914 386
UVM_INFO @ 482824980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 68238497845283193591615767309355737828027387542648208395950537002388729634091 386
UVM_INFO @ 458983854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 39518478702610480927558131680392257131120195170475793114915997582561053446353 425
UVM_INFO @ 3228226101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 46409921066027638983128935344002074723917723651920234449986345950362077697860 387
UVM_INFO @ 774028402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---