Simulation Results: aes/masked

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.20 %
  • code
  • 94.10 %
  • assert
  • 98.23 %
  • func
  • 72.28 %
  • block
  • 94.15 %
  • line
  • 95.78 %
  • branch
  • 87.07 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 4.000s 268.924us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 143.270us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 77.588us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 63.233us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 474.861us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 163.804us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 76.357us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 63.233us 1 1 100.00
aes_csr_aliasing 3.000s 163.804us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 143.270us 1 1 100.00
aes_config_error 3.000s 130.873us 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 143.270us 1 1 100.00
aes_config_error 3.000s 130.873us 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 188.901us 1 1 100.00
aes_b2b 5.000s 530.458us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 143.270us 1 1 100.00
aes_config_error 3.000s 130.873us 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
aes_alert_reset 2.000s 142.248us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 95.276us 1 1 100.00
aes_config_error 3.000s 130.873us 1 1 100.00
aes_alert_reset 2.000s 142.248us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 449.214us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 12.000s 3679.185us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 142.248us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 188.901us 1 1 100.00
aes_sideload 3.000s 126.363us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 8.000s 63.237us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 18.000s 623.427us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 78.380us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 212.782us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 212.782us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 77.588us 1 1 100.00
aes_csr_rw 2.000s 63.233us 1 1 100.00
aes_csr_aliasing 3.000s 163.804us 1 1 100.00
aes_same_csr_outstanding 7.000s 86.768us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 77.588us 1 1 100.00
aes_csr_rw 2.000s 63.233us 1 1 100.00
aes_csr_aliasing 3.000s 163.804us 1 1 100.00
aes_same_csr_outstanding 7.000s 86.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 5.000s 269.791us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 3.000s 110.494us 0 1 0.00
aes_control_fi 8.000s 10067.673us 0 1 0.00
aes_cipher_fi 3.000s 84.673us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 206.312us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 206.312us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 206.312us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 206.312us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 205.152us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 235.066us 1 1 100.00
aes_tl_intg_err 3.000s 1655.672us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 1655.672us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 142.248us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 206.312us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 206.312us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 143.270us 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
aes_alert_reset 2.000s 142.248us 1 1 100.00
aes_core_fi 48.000s 10005.008us 0 1 0.00
sec_cm_gcm_config_sparse 2 3 66.67
aes_config_error 3.000s 130.873us 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
aes_core_fi 48.000s 10005.008us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 206.312us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 90.448us 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 188.901us 1 1 100.00
aes_sideload 3.000s 126.363us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.448us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 90.448us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 90.448us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 90.448us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 90.448us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 188.901us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 110.494us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 110.494us 0 1 0.00
aes_control_fi 8.000s 10067.673us 0 1 0.00
aes_cipher_fi 3.000s 84.673us 1 1 100.00
aes_ctr_fi 2.000s 85.988us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 110.494us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 110.494us 0 1 0.00
aes_control_fi 8.000s 10067.673us 0 1 0.00
aes_cipher_fi 3.000s 84.673us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 84.673us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 110.494us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 3.000s 110.494us 0 1 0.00
aes_control_fi 8.000s 10067.673us 0 1 0.00
aes_ctr_fi 2.000s 85.988us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 110.494us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 110.494us 0 1 0.00
aes_control_fi 8.000s 10067.673us 0 1 0.00
aes_cipher_fi 3.000s 84.673us 1 1 100.00
aes_ctr_fi 2.000s 85.988us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 142.248us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 110.494us 0 1 0.00
aes_control_fi 8.000s 10067.673us 0 1 0.00
aes_cipher_fi 3.000s 84.673us 1 1 100.00
aes_ctr_fi 2.000s 85.988us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 110.494us 0 1 0.00
aes_control_fi 8.000s 10067.673us 0 1 0.00
aes_cipher_fi 3.000s 84.673us 1 1 100.00
aes_ctr_fi 2.000s 85.988us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 3.000s 110.494us 0 1 0.00
aes_control_fi 8.000s 10067.673us 0 1 0.00
aes_ctr_fi 2.000s 85.988us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 110.494us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 110.494us 0 1 0.00
aes_control_fi 8.000s 10067.673us 0 1 0.00
aes_cipher_fi 3.000s 84.673us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 26.000s 2172.083us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 51542259491687690306591686290401172565333275589101922450308854458830663607540 16336
UVM_INFO @ 269791465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 39251869455408829626458062749915836446330347542623352375926613520144522519931 778
UVM_INFO @ 2172082671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 72793207001999681113738196436628067107068280306545394611374166753978295954446 7077
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 30403871828403580133802438035058821162309372749767036502483538171878753415218 142
UVM_INFO @ 10067673110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 30329655846917054116485719501342341442301975799243354475106697382354927555291 143
UVM_INFO @ 10005008482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_stress_all 47643460868084749592919331740433340918766274566724460514040504394439250115712 77258
TEST FAILED MESSAGES DID NOT MATCH
0 9e 17 17 0
1 00 5d 5d 0