Simulation Results: aes/unmasked

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.12 %
  • code
  • 89.25 %
  • assert
  • 97.73 %
  • func
  • 74.38 %
  • block
  • 89.72 %
  • line
  • 92.18 %
  • branch
  • 80.17 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 66.671us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 97.151us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 63.732us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 68.635us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 1466.850us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 74.908us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 54.374us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 68.635us 1 1 100.00
aes_csr_aliasing 2.000s 74.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 97.151us 1 1 100.00
aes_config_error 2.000s 62.636us 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 97.151us 1 1 100.00
aes_config_error 2.000s 62.636us 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 129.788us 1 1 100.00
aes_b2b 5.000s 206.254us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 97.151us 1 1 100.00
aes_config_error 2.000s 62.636us 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
aes_alert_reset 3.000s 110.612us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 126.517us 1 1 100.00
aes_config_error 2.000s 62.636us 1 1 100.00
aes_alert_reset 3.000s 110.612us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 109.459us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 639.702us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 110.612us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 129.788us 1 1 100.00
aes_sideload 3.000s 87.404us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 70.619us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 14.000s 1346.836us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 139.019us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 129.888us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 129.888us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 63.732us 1 1 100.00
aes_csr_rw 2.000s 68.635us 1 1 100.00
aes_csr_aliasing 2.000s 74.908us 1 1 100.00
aes_same_csr_outstanding 2.000s 298.237us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 63.732us 1 1 100.00
aes_csr_rw 2.000s 68.635us 1 1 100.00
aes_csr_aliasing 2.000s 74.908us 1 1 100.00
aes_same_csr_outstanding 2.000s 298.237us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 174.090us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3.000s 200.829us 0 1 0.00
aes_control_fi 2.000s 70.374us 1 1 100.00
aes_cipher_fi 2.000s 104.931us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 212.193us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 212.193us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 212.193us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 212.193us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 272.933us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 295.196us 1 1 100.00
aes_tl_intg_err 3.000s 195.065us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 195.065us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 110.612us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 212.193us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 212.193us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 97.151us 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
aes_alert_reset 3.000s 110.612us 1 1 100.00
aes_core_fi 2.000s 103.903us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 62.636us 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
aes_core_fi 2.000s 103.903us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 212.193us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 157.974us 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 129.788us 1 1 100.00
aes_sideload 3.000s 87.404us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 157.974us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 157.974us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 157.974us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 157.974us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 157.974us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 129.788us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 200.829us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 200.829us 0 1 0.00
aes_control_fi 2.000s 70.374us 1 1 100.00
aes_cipher_fi 2.000s 104.931us 1 1 100.00
aes_ctr_fi 1.000s 73.001us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 200.829us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 200.829us 0 1 0.00
aes_control_fi 2.000s 70.374us 1 1 100.00
aes_cipher_fi 2.000s 104.931us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 104.931us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 200.829us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 200.829us 0 1 0.00
aes_control_fi 2.000s 70.374us 1 1 100.00
aes_ctr_fi 1.000s 73.001us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 200.829us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 200.829us 0 1 0.00
aes_control_fi 2.000s 70.374us 1 1 100.00
aes_cipher_fi 2.000s 104.931us 1 1 100.00
aes_ctr_fi 1.000s 73.001us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 110.612us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 200.829us 0 1 0.00
aes_control_fi 2.000s 70.374us 1 1 100.00
aes_cipher_fi 2.000s 104.931us 1 1 100.00
aes_ctr_fi 1.000s 73.001us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 200.829us 0 1 0.00
aes_control_fi 2.000s 70.374us 1 1 100.00
aes_cipher_fi 2.000s 104.931us 1 1 100.00
aes_ctr_fi 1.000s 73.001us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 200.829us 0 1 0.00
aes_control_fi 2.000s 70.374us 1 1 100.00
aes_ctr_fi 1.000s 73.001us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 200.829us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 200.829us 0 1 0.00
aes_control_fi 2.000s 70.374us 1 1 100.00
aes_cipher_fi 2.000s 104.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 1255.661us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 18255991312885693578224834538859586024589706889175634946545302228064551971899 6070
UVM_INFO @ 174089814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 16157799336588730093000216126845373738304706907338727799470017292482355391301 23486
UVM_INFO @ 1346835873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 83329826487100030856679429766979726389420353298619599236007005045193034939063 8955
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 8514277172697785406840635410064328158640571251974320220259001628150581861197 809
UVM_INFO @ 1255660783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---