Simulation Results: alert_handler

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.80 %
  • code
  • 89.33 %
  • assert
  • 98.12 %
  • func
  • 72.95 %
  • line
  • 99.68 %
  • branch
  • 97.88 %
  • cond
  • 90.36 %
  • toggle
  • 82.90 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 22.130s 1790.455us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.410s 842.184us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.390s 104.611us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 63.470s 4783.186us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 153.940s 13794.494us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.630s 66.507us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.390s 104.611us 1 1 100.00
alert_handler_csr_aliasing 153.940s 13794.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 11.960s 266.369us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 5.910s 561.041us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 888.940s 54990.533us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 6.240s 187.184us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 22.130s 1790.455us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 17.460s 368.906us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 13.880s 1044.867us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 21.410s 834.245us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 696.890s 15915.957us 1 1 100.00
alert_handler_lpg_stub_clk 841.440s 15513.521us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 384.150s 24749.743us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 4.620s 128.515us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.520s 136.717us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.110s 17.292us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.000s 171.748us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.000s 171.748us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.410s 842.184us 1 1 100.00
alert_handler_csr_rw 2.390s 104.611us 1 1 100.00
alert_handler_csr_aliasing 153.940s 13794.494us 1 1 100.00
alert_handler_same_csr_outstanding 7.220s 106.333us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.410s 842.184us 1 1 100.00
alert_handler_csr_rw 2.390s 104.611us 1 1 100.00
alert_handler_csr_aliasing 153.940s 13794.494us 1 1 100.00
alert_handler_same_csr_outstanding 7.220s 106.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 50.000s 3256.223us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 50.000s 3256.223us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 50.000s 3256.223us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 50.000s 3256.223us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 316.510s 9057.759us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
alert_handler_tl_intg_err 2.250s 92.213us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.250s 92.213us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 50.000s 3256.223us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 22.130s 1790.455us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 22.130s 1790.455us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 22.130s 1790.455us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 22.130s 1790.455us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.240s 187.184us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 696.890s 15915.957us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.240s 187.184us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 888.940s 54990.533us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 888.940s 54990.533us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 13.640s 1411.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 15.110s 1558.553us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 98536085785131863040822452892061889882585019557253101644294957257933432633464 87
UVM_INFO @ 834245272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 110608133279458405193909839243830575253327476323547387232573381117817048093524 162
UVM_INFO @ 128515080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 53404183403661834101928104382677239604254933315208068222441712208122140488111 95
UVM_INFO @ 1558552895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---