Simulation Results: chip

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.80 %
  • code
  • 84.29 %
  • assert
  • 97.49 %
  • func
  • 48.61 %
  • line
  • 94.25 %
  • branch
  • 93.62 %
  • cond
  • 89.10 %
  • toggle
  • 87.32 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
76.90%
V2S
50.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 93.640s 2274.905us 1 1 100.00
chip_sw_example_rom 71.360s 2521.957us 1 1 100.00
chip_sw_example_manufacturer 160.700s 2600.091us 1 1 100.00
chip_sw_example_concurrency 143.340s 2672.602us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 134.500s 3670.519us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 343.590s 4827.376us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 464.670s 6325.591us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4528.590s 36710.594us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 47.720s 1625.887us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4528.590s 36710.594us 1 1 100.00
chip_csr_rw 343.590s 4827.376us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.980s 204.779us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 297.860s 4005.190us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 297.860s 4005.190us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 297.860s 4005.190us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 427.200s 4512.957us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 427.200s 4512.957us 1 1 100.00
chip_sw_uart_tx_rx_idx1 365.680s 5029.536us 1 1 100.00
chip_sw_uart_tx_rx_idx2 355.510s 4301.942us 1 1 100.00
chip_sw_uart_tx_rx_idx3 376.320s 4904.876us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1007.770s 8367.524us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1061.130s 9001.513us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 613.790s 8382.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 184.190s 5361.658us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 184.190s 5361.658us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 193.000s 3189.250us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 184.290s 3481.605us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 176.530s 3684.572us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 159.010s 3268.395us 1 1 100.00
chip_tap_straps_testunlock0 94.300s 3142.789us 1 1 100.00
chip_tap_straps_rma 292.130s 5378.377us 1 1 100.00
chip_tap_straps_prod 961.550s 13999.095us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 463.200s 6214.977us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 463.200s 6214.977us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 568.110s 7915.889us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 725.620s 10372.830us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.890s 4470.394us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 534.550s 5348.804us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3953.090s 18734.300us 1 1 100.00
chip_sw_aes_enc_jitter_en 150.140s 3368.398us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 544.190s 7149.230us 1 1 100.00
chip_sw_hmac_enc_jitter_en 146.150s 3263.091us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1143.940s 10148.858us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 149.740s 3047.147us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 450.900s 5735.045us 1 1 100.00
chip_sw_clkmgr_jitter 167.860s 2797.513us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 215.080s 2874.562us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 454.520s 7778.538us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 260.060s 5074.835us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 162.230s 2401.536us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 260.060s 5074.835us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 169.290s 2648.164us 1 1 100.00
chip_sw_aes_smoketest 171.630s 3133.590us 1 1 100.00
chip_sw_aon_timer_smoketest 189.910s 3134.549us 1 1 100.00
chip_sw_clkmgr_smoketest 120.830s 3035.856us 1 1 100.00
chip_sw_csrng_smoketest 100.750s 2571.371us 1 1 100.00
chip_sw_entropy_src_smoketest 886.790s 7160.731us 1 1 100.00
chip_sw_gpio_smoketest 207.830s 3361.232us 1 1 100.00
chip_sw_hmac_smoketest 219.700s 3583.971us 1 1 100.00
chip_sw_kmac_smoketest 213.460s 3347.534us 1 1 100.00
chip_sw_otbn_smoketest 1476.420s 10831.792us 1 1 100.00
chip_sw_pwrmgr_smoketest 279.000s 6133.683us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 236.200s 5936.286us 1 1 100.00
chip_sw_rv_plic_smoketest 125.370s 2775.155us 1 1 100.00
chip_sw_rv_timer_smoketest 196.160s 3335.796us 1 1 100.00
chip_sw_rstmgr_smoketest 131.930s 3157.052us 1 1 100.00
chip_sw_sram_ctrl_smoketest 147.350s 3274.591us 1 1 100.00
chip_sw_uart_smoketest 178.980s 3383.977us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 169.950s 2955.166us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 372.060s 4823.779us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7774.320s 60311.891us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3186.820s 17624.074us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 20.511s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1137.100s 14749.786us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 956.510s 14939.029us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7094.830s 52773.484us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7209.040s 56016.896us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 62.620s 2539.029us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 62.620s 2539.029us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4528.590s 36710.594us 1 1 100.00
chip_same_csr_outstanding 1542.020s 14928.361us 1 1 100.00
chip_csr_hw_reset 134.500s 3670.519us 1 1 100.00
chip_csr_rw 343.590s 4827.376us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4528.590s 36710.594us 1 1 100.00
chip_same_csr_outstanding 1542.020s 14928.361us 1 1 100.00
chip_csr_hw_reset 134.500s 3670.519us 1 1 100.00
chip_csr_rw 343.590s 4827.376us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 14.660s 152.323us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.000s 54.635us 1 1 100.00
xbar_smoke_large_delays 40.070s 7126.262us 1 1 100.00
xbar_smoke_slow_rsp 48.530s 5907.952us 1 1 100.00
xbar_random_zero_delays 6.210s 52.385us 1 1 100.00
xbar_random_large_delays 37.070s 5826.112us 1 1 100.00
xbar_random_slow_rsp 236.600s 27079.524us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 8.870s 194.478us 1 1 100.00
xbar_error_and_unmapped_addr 29.240s 979.692us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 32.060s 1375.060us 1 1 100.00
xbar_error_and_unmapped_addr 29.240s 979.692us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 59.010s 2247.443us 1 1 100.00
xbar_access_same_device_slow_rsp 25.800s 2689.014us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 28.430s 1450.632us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 92.650s 1585.175us 1 1 100.00
xbar_stress_all_with_error 65.530s 2941.932us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 274.010s 8145.102us 1 1 100.00
xbar_stress_all_with_reset_error 174.260s 3287.492us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3186.820s 17624.074us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 456.280s 9638.349us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 419.150s 4900.502us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 103.108s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 54.229s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 9.736s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 15.384s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 16.080s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 34.688s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 13.678s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 26.270s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 11.779s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 12.389s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 129.217s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 42.637s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 24.536s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 13.590s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 11.073s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 20.760s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 22.060s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 21.170s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 21.140s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 20.320s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 18.010s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 20.320s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 22.370s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 23.250s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 20.230s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 18.210s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 19.240s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 20.850s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.310s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.240s 10.160us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 54.757s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 67.213s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 59.453s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 58.551s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 50.427s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 6039.580s 30700.793us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 5866.530s 28193.464us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5790.290s 28194.835us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3127.600s 15437.460us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2735.000s 34575.543us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2735.000s 34575.543us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 186.840s 2985.400us 1 1 100.00
chip_sw_aes_enc_jitter_en 150.140s 3368.398us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 143.670s 2744.121us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 161.650s 2762.889us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1288.330s 10412.764us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 130.620s 3358.126us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 372.530s 5762.661us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 349.550s 5600.218us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 482.440s 4953.958us 1 1 100.00
chip_plic_all_irqs_10 217.100s 3360.054us 1 1 100.00
chip_plic_all_irqs_20 346.500s 4234.106us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 142.450s 2511.029us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1184.360s 11887.172us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 199.380s 4101.688us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 175.540s 3265.308us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.136s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 879.660s 7154.154us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1020.390s 7906.800us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 643.320s 7726.677us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8175.220s 255526.900us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 268.140s 4893.840us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 279.000s 6133.683us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 268.140s 4893.840us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 499.660s 7970.213us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 499.660s 7970.213us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 253.640s 7718.898us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 348.490s 5288.918us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 614.940s 5724.942us 1 1 100.00
chip_sw_aes_idle 161.650s 2762.889us 1 1 100.00
chip_sw_hmac_enc_idle 168.290s 2920.702us 1 1 100.00
chip_sw_kmac_idle 128.280s 2501.550us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 306.950s 4742.433us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 286.840s 4012.503us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 251.930s 3712.525us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 233.170s 4259.711us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 631.760s 10643.698us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 374.520s 4385.594us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 312.940s 4886.030us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 355.590s 4466.188us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 355.260s 5312.111us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 319.590s 4437.051us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 329.010s 4906.293us 1 1 100.00
chip_sw_ast_clk_outputs 568.110s 7915.889us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 494.680s 12965.098us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 355.590s 4466.188us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 355.260s 5312.111us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.890s 4470.394us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 534.550s 5348.804us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3953.090s 18734.300us 1 1 100.00
chip_sw_aes_enc_jitter_en 150.140s 3368.398us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 544.190s 7149.230us 1 1 100.00
chip_sw_hmac_enc_jitter_en 146.150s 3263.091us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1143.940s 10148.858us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 149.740s 3047.147us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 450.900s 5735.045us 1 1 100.00
chip_sw_clkmgr_jitter 167.860s 2797.513us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 121.390s 2830.546us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 370.230s 5481.327us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 577.890s 6735.369us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3984.330s 24808.099us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 168.420s 3110.854us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 160.950s 3680.245us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 981.410s 10302.997us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 174.940s 2865.706us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 434.570s 5720.349us 1 1 100.00
chip_sw_flash_init_reduced_freq 1172.600s 20414.167us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 14727.160s 176742.160us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 568.110s 7915.889us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 302.410s 4871.194us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 214.630s 3471.100us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 349.550s 5600.218us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 879.660s 7154.154us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2207.260s 24666.843us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 275.270s 4683.515us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 398.060s 6751.441us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 170.810s 3521.905us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 2681.830s 15799.039us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 136.370s 2771.453us 1 1 100.00
chip_sw_edn_entropy_reqs 803.460s 7877.879us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 136.370s 2771.453us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2207.260s 24666.843us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 134.490s 3031.882us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1403.420s 21073.417us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 427.790s 5177.092us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 534.550s 5348.804us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 301.950s 4131.463us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.890s 4470.394us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3123.580s 44892.906us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1403.420s 21073.417us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 171.220s 3652.017us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 763.310s 7535.773us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 172.210s 2740.443us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3123.580s 44892.906us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 172.210s 2740.443us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 172.210s 2740.443us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 172.210s 2740.443us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 172.210s 2740.443us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 349.550s 5600.218us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 82.670s 3794.471us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 536.020s 5856.828us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 413.720s 5078.030us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 413.720s 5078.030us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 146.690s 2526.883us 1 1 100.00
chip_sw_hmac_enc_jitter_en 146.150s 3263.091us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 168.290s 2920.702us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1437.210s 11536.510us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1583.460s 12018.454us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 377.980s 4935.987us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 375.190s 5152.275us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 441.270s 5518.421us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 283.830s 3938.211us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 763.310s 7535.773us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1143.940s 10148.858us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1522.870s 11836.647us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1288.330s 10412.764us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4393.080s 20026.791us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 167.740s 2674.566us 1 1 100.00
chip_sw_kmac_mode_kmac 160.350s 3094.830us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 149.740s 3047.147us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 763.310s 7535.773us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 746.570s 13373.933us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 143.450s 2942.316us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 570.220s 6085.229us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 128.280s 2501.550us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 372.530s 5762.661us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 159.010s 3268.395us 1 1 100.00
chip_tap_straps_rma 292.130s 5378.377us 1 1 100.00
chip_tap_straps_prod 961.550s 13999.095us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 194.570s 3670.791us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 746.570s 13373.933us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 746.570s 13373.933us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 746.570s 13373.933us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 790.730s 7598.719us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 172.210s 2740.443us 0 1 0.00
chip_sw_flash_rma_unlocked 3123.580s 44892.906us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 170.010s 3298.813us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 448.360s 7383.728us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 564.640s 7252.346us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 467.040s 6138.276us 0 1 0.00
chip_sw_lc_ctrl_transition 746.570s 13373.933us 1 1 100.00
chip_sw_keymgr_key_derivation 763.310s 7535.773us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 352.370s 8458.560us 1 1 100.00
chip_sw_sram_ctrl_execution_main 485.880s 7251.336us 1 1 100.00
chip_prim_tl_access 82.670s 3794.471us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 494.680s 12965.098us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 374.520s 4385.594us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 312.940s 4886.030us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 355.590s 4466.188us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 355.260s 5312.111us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 319.590s 4437.051us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 329.010s 4906.293us 1 1 100.00
chip_tap_straps_dev 159.010s 3268.395us 1 1 100.00
chip_tap_straps_rma 292.130s 5378.377us 1 1 100.00
chip_tap_straps_prod 961.550s 13999.095us 1 1 100.00
chip_rv_dm_lc_disabled 247.540s 9347.906us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 179.390s 3901.359us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 72.880s 2784.385us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 94.520s 2735.035us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 73.120s 3176.979us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1934.580s 35540.096us 1 1 100.00
chip_rv_dm_lc_disabled 247.540s 9347.906us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 547.910s 11590.132us 0 1 0.00
chip_sw_lc_walkthrough_prod 526.550s 8209.106us 0 1 0.00
chip_sw_lc_walkthrough_prodend 541.110s 11140.781us 1 1 100.00
chip_sw_lc_walkthrough_rma 313.820s 7129.186us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1934.580s 35540.096us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 59.130s 2205.834us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 63.070s 2996.489us 1 1 100.00
rom_volatile_raw_unlock 13.695s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3888.870s 18030.061us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3953.090s 18734.300us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 614.940s 5724.942us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 614.940s 5724.942us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 614.940s 5724.942us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 319.340s 3893.302us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 746.570s 13373.933us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1403.420s 21073.417us 1 1 100.00
chip_sw_otbn_mem_scramble 319.340s 3893.302us 1 1 100.00
chip_sw_keymgr_key_derivation 763.310s 7535.773us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 306.650s 3879.211us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 154.570s 2451.701us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1403.420s 21073.417us 1 1 100.00
chip_sw_otbn_mem_scramble 319.340s 3893.302us 1 1 100.00
chip_sw_keymgr_key_derivation 763.310s 7535.773us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 306.650s 3879.211us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 154.570s 2451.701us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 746.570s 13373.933us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 280.700s 4433.429us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 194.570s 3670.791us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 170.010s 3298.813us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 448.360s 7383.728us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 564.640s 7252.346us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 467.040s 6138.276us 0 1 0.00
chip_sw_lc_ctrl_transition 746.570s 13373.933us 1 1 100.00
chip_prim_tl_access 82.670s 3794.471us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 82.670s 3794.471us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 865.670s 6911.509us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 219.380s 5980.451us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1011.600s 25469.718us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 238.040s 7131.812us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 323.220s 7691.524us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 439.300s 6627.249us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 753.970s 19522.161us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 925.430s 13638.058us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 499.660s 7970.213us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 735.430s 12613.560us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 310.150s 4029.852us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 219.380s 5980.451us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 237.590s 4792.151us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1208.450s 15510.434us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 327.790s 7184.833us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 152.490s 3196.890us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1083.930s 16247.567us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 824.890s 9420.789us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 947.320s 10103.701us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1523.080s 25190.468us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 124.240s 2374.754us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 349.550s 5600.218us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 352.370s 8458.560us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 352.370s 8458.560us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 947.320s 10103.701us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1083.930s 16247.567us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 310.150s 4029.852us 1 1 100.00
chip_sw_pwrmgr_smoketest 279.000s 6133.683us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 211.770s 4865.581us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 549.130s 8035.119us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 273.450s 4084.856us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1184.360s 11887.172us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 190.960s 3285.393us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 349.550s 5600.218us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1020.390s 7906.800us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 404.780s 4581.502us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 483.440s 5423.647us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 185.790s 3374.771us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 154.570s 2451.701us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 549.130s 8035.119us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 549.130s 8035.119us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 138.400s 2516.950us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1087.800s 16227.994us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 756.750s 13812.307us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 211.770s 4865.581us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 175.170s 3264.197us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1313.750s 13457.773us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 292.130s 5378.377us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 247.540s 9347.906us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 482.440s 4953.958us 1 1 100.00
chip_plic_all_irqs_10 217.100s 3360.054us 1 1 100.00
chip_plic_all_irqs_20 346.500s 4234.106us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 159.770s 2734.717us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 154.860s 2715.371us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3186.820s 17624.074us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 269.370s 4487.000us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 198.860s 3317.194us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 237.920s 3795.967us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 163.270s 3578.879us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 306.650s 3879.211us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 450.900s 5735.045us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 465.140s 8842.580us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 474.570s 7412.331us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 485.880s 7251.336us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 349.550s 5600.218us 1 1 100.00
chip_sw_data_integrity_escalation 463.200s 6214.977us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 824.890s 9420.789us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1082.690s 22461.222us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 151.010s 3093.121us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 264.700s 3974.929us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 306.850s 4950.247us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1082.690s 22461.222us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1082.690s 22461.222us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1993.800s 19971.855us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1993.800s 19971.855us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 383.610s 7346.964us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2735.000s 34575.543us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 144.950s 2968.370us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 154.020s 3454.093us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 260.360s 4347.468us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 296.480s 3766.011us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 912.360s 7780.019us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4931.260s 31650.575us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1830.320s 12228.700us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 197.390s 3202.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 167.660s 3054.112us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 85.510s 2493.858us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9719.470s 68250.702us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1178.110s 6431.664us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 206.440s 4384.129us 0 1 0.00
rom_e2e_jtag_debug_dev 455.820s 6284.957us 0 1 0.00
rom_e2e_jtag_debug_rma 185.640s 4999.173us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 77.940s 2109.403us 0 1 0.00
rom_e2e_jtag_inject_dev 58.850s 2716.889us 0 1 0.00
rom_e2e_jtag_inject_rma 59.020s 2185.719us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 26.740s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 210.520s 3004.892us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 345.100s 3310.423us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 777.670s 5401.055us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 873.350s 7475.563us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 208.250s 2894.748us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 575.940s 5467.891us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 51.520s 2415.649us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 201.180s 3021.443us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 260.910s 5645.049us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 295.480s 5469.727us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 947.320s 10103.701us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 206.440s 4384.129us 0 1 0.00
rom_e2e_jtag_debug_dev 455.820s 6284.957us 0 1 0.00
rom_e2e_jtag_debug_rma 185.640s 4999.173us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 443.240s 6582.537us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 349.550s 5600.218us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5438.260s 38508.221us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5438.260s 38508.221us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 200.870s 3757.575us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 427.200s 4512.957us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2685.450s 18736.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 169.130s 3110.541us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 19.470s 10.120us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 5.150s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 177.250s 2628.494us 1 1 100.00
chip_sw_otp_ctrl_descrambling 170.430s 2993.623us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 237.780s 4152.559us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.947s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 159.180s 2761.963us 1 1 100.00
ate_bootstrap_flash_erase 716.450s 10010.200us 0 1 0.00
ate_bootstrap_one_frame 6018.360s 43882.975us 1 1 100.00
ate_bootstrap_disjoint 9143.020s 79769.975us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 74756934630368435290798110358267833527987458637793306382789424271159572738397 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 72024901177701993192320161923258807611087632000760999735362042592443399724722 None
Another command (pid=552620) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=531743) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=460683) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 21412023793689459248187809184697940853426927129445985212530797668069856576575 None
Another command (pid=627179) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=665382) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=638485) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 105306294580955235851836079094523131747624027742100834126799859486556517281531 None
---- STDERR ----
Another command (pid=561369) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 92063842967236588083929869235494634874870960408553689295621034565750233666477 None
Another command (pid=577907) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=576262) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=581168) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 4204134070714833002763446954893152743017433513762890484990500852008561837057 None
Another command (pid=576262) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=581168) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=563093) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 71570094408036113175765995693899837673195454093441778679733785410305799370606 None
---- STDERR ----
Another command (pid=369576) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=379642) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 25736539023075716356774069460127571625531642503871475869937426168063045863221 None
Another command (pid=561369) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=454739) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=575083) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 109350192194256260899418239500884445025438295370892257801452039735756623609431 None
Another command (pid=593289) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=443908) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=579223) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 20022761848081758798719786431405944991555555111890104149458643470002828348013 None
---- STDERR ----
Another command (pid=561369) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=454739) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 93868804094927656345440136644270332982573613210698347801859784813370498945989 None
Another command (pid=454739) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=575083) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=459713) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 48677083450259865607844513221899002808519208867773947253842683968195449018428 None
Another command (pid=554603) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=451938) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=483479) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 80011462836219988994850060111593092554121838897526813751540357742876561074539 None
---- STDERR ----
Another command (pid=416891) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=548495) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 72688261229952647985183665260320880577231752374425682988649943974010088147463 None
---- STDERR ----
Another command (pid=451938) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=483479) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 115306915756914627401472077084765050465351650373147438241134865641941327625018 None
---- STDERR ----
Another command (pid=558148) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 56111760446569954955450801433297270893680574404397621895849086987839906626724 None
Another command (pid=556887) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=558148) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=560811) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 2226073893552299569329239200421829673954618000098548236122108105904827399760 None
---- STDERR ----
Another command (pid=369576) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=379642) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 58592633337099432098459580927994486024085919673555548051267159525026322985766 None
Another command (pid=460683) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=509431) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=548495) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 106662829650832674851561054463996330886803732113067040279668684853742317749314 None
---- STDERR ----
Another command (pid=460257) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=475706) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 114302224414516001862883608890110912538902191259015379252184722122455918319436 None
Another command (pid=475706) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=552620) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=451938) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 69941034801434416167905558478463936442726937538947463578133849784045264279586 None
Another command (pid=416891) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=548495) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=559105) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 48668091038560715599231737520553914191386733957258307147702676789872618499749 None
---- STDERR ----
Another command (pid=373936) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 43993229467808715304176904881049016411216372866331850095861692286440993397489 None
Another command (pid=382847) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=373936) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=431136) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 99467499384898994992776148755044376784748809914154919188762945380314728222439 None
Another command (pid=382847) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=373936) is running. Waiting for it to complete on the server (server_pid=273325)...
Another command (pid=431136) is running. Waiting for it to complete on the server (server_pid=273325)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 14898336361130627070435818059075056559337227240743729161984764395633396695492 332
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 13238884378312597686476356835690574578263309687028189388085045035300401547640 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 45757403294557572516647560487296449657633329703468827089467071872289768407321 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 13532386066736478431302210339692485486709758605787867814716702175750046023691 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 20056648622817585972451328784637279777150916669791795758921949124224812129501 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 114854955196011579654824012396065092574590902885018190937105556580307729239528 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 76708379970143088067073942663757555521299837537469723413985270642191736466575 365
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 12397628239829714852660346296214026337897430847149338940243484134601559933283 368
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 38437396090657526174359946142324515549297616195865629959117285555152761263050 364
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 24222387723686423330283582837587124640368430936790332854558199373730285647588 328
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 90186116504004995573996566423251324349146920745424110827332616054635808045353 326
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 9018530239221218874913399414352071456887114264940402615008335844634243193279 328
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 35336155366504651007818832829449276217186632358861984590078672403086177250907 369
UVM_INFO @ 11590.132466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 11952707904778153012162158425753466845744629369086675227426742498558599642783 369
UVM_INFO @ 8209.105567 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 103681144272146868855470562735000415139181812190989696011834974455464586495692 341
UVM_INFO @ 7129.186220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 29384983311880441144499161698182307275764286304056803787230285738355920207803 327
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 10255805030982879224090763413270564064540542774318912289829733440697184558795 326
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 50415559292618468198780418606727543039704393544355312338001589737262477103968 326
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 53001167587451800710407115001917340943251431071939922132725455183947953425854 318
UVM_ERROR @ 3196.890350 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3196.890350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 9072678869766036978334157548757403960152547428833962512664353693981815665080 365
UVM_ERROR @ 15510.434260 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 15510.434260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 27387157717369296103153426331855514341635704697384843929043794403784649996450 342
UVM_INFO @ 12018.454467 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 29680218096439999277130115560751929254727332908902865628977827848276766946008 334
UVM_INFO @ 20026.790952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 55827029024133591836157599729289725994605472409483348242488467572564071990483 217
TL item was: req: (cip_tl_seq_item@30974) { a_addr: 'h107a8 a_data: 'h17e15b76 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h1a575 d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2539.028803 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 13552826008661898306645696688712955732058777979182639419616776690004507390134 224
TL item was: req: (cip_tl_seq_item@30356) { a_addr: 'h10640 a_data: 'hf4f7b6ca a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h1b606 d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1625.886704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 40364560237064878553958741726117807001799385086994845980295305762063702833932 364
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 5790616101112683964493906294898078267483976573193094267428573648573987043886 326
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 81469161927914394275616456727186552974989516324184739569351759251976730020087 364
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 48008793509832451971692590420304844800475170173800658888233309593068111608678 328
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 43669947557009572744651118885533186315537744606199980782782733093567339871092 301
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 92465804603167383180628500949411737046860021797079590497065428493548748530983 332
UVM_INFO @ 3317.193687 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 62331723420856916483885000197008043215798522534841393412470040107058423670636 314
UVM_INFO @ 2740.442969 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 79650825567451412266919025833577447761873277663884335754596108154652798760633 347
UVM_INFO @ 6138.275645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 23855400296874639844394361767693347815024106541680342909232748474591314444527 321
UVM_ERROR @ 3021.442524 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3021.442524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 33661651640336981537212715245110859414971371368453463147516235802349836159535 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 56354420331376677440340653879207428233839765652893576665909649119398210396788 327
UVM_ERROR @ 5980.450998 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5980.450998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' 1 test run
chip_sw_pwrmgr_random_sleep_all_reset_reqs 79107968313478019693773462536502249279934020218756635719847260318952891229049 389
UVM_ERROR @ 16247.566888 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 16247.566888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 1 test run
chip_sw_pwrmgr_deep_sleep_por_reset 9876978790783090975968917620721543135773383200922765616429646448742806948568 330
UVM_ERROR @ 7691.523500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7691.523500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 37446050125635924028382139757244760245103365422433385876971363447130346127537 332
UVM_INFO @ 34575.542857 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:342)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 107554046078624047207263911881678483117343479036818287776174801665456018659916 312
UVM_INFO @ 3358.125932 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 46268194048550454743352499777137316908228266240842566020702038336477333451707 308
UVM_INFO @ 3265.307569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 52747033264282929168217717402272349101857988741978985863515329288057336123500 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 92698512439391258544995045627627274842361054354235252076356561287216683471384 348
UVM_INFO @ 3004.892350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 31561228936138472721572581202052123768393045369382494131407716432145295642273 334
UVM_INFO @ 13457.773078 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 52569324475732439894181215869776045581359583421291992712993049164874367323847 267
UVM_INFO @ 9347.906256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 39518142474785721422642189056212132466466759154494926093707323405819199636473 329
UVM_INFO @ 2493.857840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 12172365406402912919945017808593698051742587019960796851312309433239560302300 323
UVM_INFO @ 14749.786492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 36271565853523820027618474168750790560773420177949657277743359786921607892949 334
UVM_INFO @ 14939.029018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 12151564897651834666419648121624062399076555281672419410448855647205280420798 327
UVM_INFO @ 10372.830278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 34357873915057743601954104142140392699018963417225612584918474139922316925342 272
UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_exception_c 44257227263070339206998162038338538897651921563577790007096108327984184885049 319
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 4900.501501 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_output 20896875792535112181903070588843789309688328698654840507516542655719961199868 312
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 9638.348553 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 95575029383317822677148481079160967491878675272349469834824610923467796047249 326
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 89702525997075610278097414923053815619262811415360982822923374213410152046447 326
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds 1 test run
rom_e2e_jtag_debug_rma 99631724777979413292883387728673551620222350032991933642844119042938561160096 318
UVM_INFO @ 4999.172824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 67433183324000317091690652616285274601256315268507592881291072874346999159900 327
UVM_ERROR @ 4823.779391 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4823.779391 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---