Simulation Results: clkmgr

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.97 %
  • code
  • 98.12 %
  • assert
  • 95.20 %
  • func
  • 85.59 %
  • line
  • 98.97 %
  • branch
  • 98.64 %
  • cond
  • 93.78 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.840s 27.098us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.790s 37.343us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.910s 131.914us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.440s 287.239us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.160s 42.117us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.890s 76.748us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.910s 131.914us 1 1 100.00
clkmgr_csr_aliasing 1.160s 42.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.760s 45.209us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.590s 228.779us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.800s 57.556us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.700s 39.921us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.840s 27.098us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 4.990s 1659.639us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.040s 1045.181us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 4.990s 1659.639us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 10.610s 4247.130us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.710s 17.343us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.470s 32.284us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.470s 32.284us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.790s 37.343us 1 1 100.00
clkmgr_csr_rw 0.910s 131.914us 1 1 100.00
clkmgr_csr_aliasing 1.160s 42.117us 1 1 100.00
clkmgr_same_csr_outstanding 0.980s 72.710us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.790s 37.343us 1 1 100.00
clkmgr_csr_rw 0.910s 131.914us 1 1 100.00
clkmgr_csr_aliasing 1.160s 42.117us 1 1 100.00
clkmgr_same_csr_outstanding 0.980s 72.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 42.460s 10033.089us 0 1 0.00
clkmgr_tl_intg_err 2.350s 245.342us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 67.928us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 67.928us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 67.928us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 67.928us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 11.140s 2019.788us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.350s 245.342us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 4.990s 1659.639us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.040s 1045.181us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.110s 67.928us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.770s 37.341us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.810s 32.077us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.850s 26.971us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.780s 29.108us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.510s 380.207us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.910s 131.914us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 42.460s 10033.089us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.910s 131.914us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.910s 131.914us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 42.460s 10033.089us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.540s 944.520us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 113.370s 25470.617us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.measure_ctrl_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 79512295356528216888520689239579255331851895608437006079056538331349949779033 75
UVM_INFO @ 2019787988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 82921708815171890322107884282173720268837183018039449866598176711512363220747 97
UVM_INFO @ 10033089317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---